437 lines
8.9 KiB
C
437 lines
8.9 KiB
C
/*
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* This file is part of the UCB release of Plan 9. It is subject to the license
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* terms in the LICENSE file found in the top-level directory of this
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* distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
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* part of the UCB release of Plan 9, including this file, may be copied,
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* modified, propagated, or distributed except according to the terms contained
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* in the LICENSE file.
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*/
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#include <u.h>
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#include <lib9.h>
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#include <bio.h>
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#include "pci.h"
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#include "vga.h"
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/*
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* PCI support code.
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* There really should be a driver for this, it's not terribly safe
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* without locks or restrictions on what can be poked (e.g. Axil NX801).
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*/
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enum { /* configuration mechanism #1 */
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PciADDR = 0xCF8, /* CONFIG_ADDRESS */
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PciDATA = 0xCFC, /* CONFIG_DATA */
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/* configuration mechanism #2 */
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PciCSE = 0xCF8, /* configuration space enable */
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PciFORWARD = 0xCFA, /* which bus */
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MaxFNO = 7,
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MaxUBN = 255,
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};
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static int pcicfgmode = -1;
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static int pcimaxdno;
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static Pcidev* pciroot;
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static Pcidev* pcilist;
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static Pcidev* pcitail;
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static int pcicfgrw32(int, int, int, int);
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static int
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pciscan(int bno, Pcidev** list)
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{
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uint32_t v;
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Pcidev *p, *head, *tail;
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int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
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maxubn = bno;
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head = nil;
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tail = nil;
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for(dno = 0; dno <= pcimaxdno; dno++){
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maxfno = 0;
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for(fno = 0; fno <= maxfno; fno++){
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/*
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* For this possible device, form the bus+device+function
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* triplet needed to address it and try to read the vendor
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* and device ID. If successful, allocate a device struct
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* and start to fill it in with some useful information from
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* the device's configuration space.
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*/
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tbdf = MKBUS(BusPCI, bno, dno, fno);
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l = pcicfgrw32(tbdf, PciVID, 0, 1);
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if(l == 0xFFFFFFFF || l == 0)
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continue;
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p = mallocz(sizeof(*p), 1);
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p->tbdf = tbdf;
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p->vid = l;
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p->did = l>>16;
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p->rid = pcicfgr8(p, PciRID);
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if(pcilist != nil)
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pcitail->list = p;
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else
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pcilist = p;
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pcitail = p;
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p->intl = pcicfgr8(p, PciINTL);
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p->ccru = pcicfgr16(p, PciCCRu);
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/*
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* If the device is a multi-function device adjust the
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* loop count so all possible functions are checked.
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*/
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hdt = pcicfgr8(p, PciHDT);
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if(hdt & 0x80)
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maxfno = MaxFNO;
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/*
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* If appropriate, read the base address registers
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* and work out the sizes.
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*/
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switch(p->ccru>>8){
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case 0x01: /* mass storage controller */
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case 0x02: /* network controller */
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case 0x03: /* display controller */
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case 0x04: /* multimedia device */
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case 0x07: /* simple communication controllers */
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case 0x08: /* base system peripherals */
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case 0x09: /* input devices */
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case 0x0A: /* docking stations */
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case 0x0B: /* processors */
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case 0x0C: /* serial bus controllers */
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if((hdt & 0x7F) != 0)
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break;
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rno = PciBAR0 - 4;
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for(i = 0; i < nelem(p->mem); i++){
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rno += 4;
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p->mem[i].bar = pcicfgr32(p, rno);
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pcicfgw32(p, rno, -1);
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v = pcicfgr32(p, rno);
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pcicfgw32(p, rno, p->mem[i].bar);
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p->mem[i].size = -(v & ~0xF);
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}
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break;
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case 0x00:
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case 0x05: /* memory controller */
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case 0x06: /* bridge device */
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default:
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break;
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}
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if(head != nil)
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tail->link = p;
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else
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head = p;
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tail = p;
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}
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}
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*list = head;
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for(p = head; p != nil; p = p->link){
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/*
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* Find PCI-PCI bridges and recursively descend the tree.
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*/
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if(p->ccru != ((0x06<<8)|0x04))
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continue;
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/*
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* If the secondary or subordinate bus number is not initialised
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* try to do what the PCI BIOS should have done and fill in the
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* numbers as the tree is descended. On the way down the subordinate
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* bus number is set to the maximum as it's not known how many
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* buses are behind this one; the final value is set on the way
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* back up.
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*/
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sbn = pcicfgr8(p, PciSBN);
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ubn = pcicfgr8(p, PciUBN);
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if(sbn == 0 || ubn == 0){
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sbn = maxubn+1;
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/*
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* Make sure memory, I/O and master enables are off,
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* set the primary, secondary and subordinate bus numbers
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* and clear the secondary status before attempting to
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* scan the secondary bus.
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*
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* Initialisation of the bridge should be done here.
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*/
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pcicfgw32(p, PciPCR, 0xFFFF0000);
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l = (MaxUBN<<16)|(sbn<<8)|bno;
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pcicfgw32(p, PciPBN, l);
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pcicfgw16(p, PciSPSR, 0xFFFF);
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maxubn = pciscan(sbn, &p->bridge);
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l = (maxubn<<16)|(sbn<<8)|bno;
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pcicfgw32(p, PciPBN, l);
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}
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else{
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maxubn = ubn;
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pciscan(sbn, &p->bridge);
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}
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}
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return maxubn;
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}
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static void
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pcicfginit(void)
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{
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#ifdef kernel
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char *p;
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#endif /* kernel */
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int bno;
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Pcidev **list;
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if(pcicfgmode == -1){
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/*
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* Try to determine which PCI configuration mode is implemented.
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* Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
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* a DWORD at 0xCF8 and another at 0xCFC and will pass through
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* any non-DWORD accesses as normal I/O cycles. There shouldn't be
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* a device behind these addresses so if Mode2 accesses fail try
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* for Mode1 (which is preferred, Mode2 is deprecated).
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*/
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outportb(PciCSE, 0);
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if(inportb(PciCSE) == 0){
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pcicfgmode = 2;
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pcimaxdno = 15;
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}
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else{
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outportl(PciADDR, 0);
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if(inportl(PciADDR) == 0){
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pcicfgmode = 1;
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pcimaxdno = 31;
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}
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}
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if(pcicfgmode > 0){
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list = &pciroot;
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for(bno = 0; bno < 256; bno++){
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bno = pciscan(bno, list);
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while(*list)
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list = &(*list)->link;
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}
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}
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}
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}
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static int
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pcicfgrw8(int tbdf, int rno, int data, int read)
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{
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int o, type, x;
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if(pcicfgmode == -1)
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pcicfginit();
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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x = -1;
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if(BUSDNO(tbdf) > pcimaxdno)
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return x;
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switch(pcicfgmode){
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case 1:
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o = rno & 0x03;
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rno &= ~0x03;
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outportl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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if(read)
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x = inportb(PciDATA+o);
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else
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outportb(PciDATA+o, data);
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outportl(PciADDR, 0);
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break;
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case 2:
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outportb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
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outportb(PciFORWARD, BUSBNO(tbdf));
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if(read)
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x = inportb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
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else
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outportb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
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outportb(PciCSE, 0);
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break;
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}
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return x;
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}
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int
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pcicfgr8(Pcidev* pcidev, int rno)
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{
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return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
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}
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void
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pcicfgw8(Pcidev* pcidev, int rno, int data)
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{
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pcicfgrw8(pcidev->tbdf, rno, data, 0);
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}
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static int
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pcicfgrw16(int tbdf, int rno, int data, int read)
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{
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int o, type, x;
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if(pcicfgmode == -1)
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pcicfginit();
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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x = -1;
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if(BUSDNO(tbdf) > pcimaxdno)
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return x;
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switch(pcicfgmode){
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case 1:
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o = rno & 0x02;
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rno &= ~0x03;
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outportl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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if(read)
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x = inportw(PciDATA+o);
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else
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outportw(PciDATA+o, data);
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outportl(PciADDR, 0);
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break;
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case 2:
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outportb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
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outportb(PciFORWARD, BUSBNO(tbdf));
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if(read)
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x = inportw((0xC000|(BUSDNO(tbdf)<<8)) + rno);
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else
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outportw((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
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outportb(PciCSE, 0);
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break;
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}
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return x;
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}
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int
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pcicfgr16(Pcidev* pcidev, int rno)
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{
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return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
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}
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void
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pcicfgw16(Pcidev* pcidev, int rno, int data)
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{
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pcicfgrw16(pcidev->tbdf, rno, data, 0);
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}
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static int
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pcicfgrw32(int tbdf, int rno, int data, int read)
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{
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int type, x;
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if(pcicfgmode == -1)
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pcicfginit();
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if(BUSBNO(tbdf))
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type = 0x01;
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else
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type = 0x00;
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x = -1;
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if(BUSDNO(tbdf) > pcimaxdno)
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return x;
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switch(pcicfgmode){
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case 1:
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rno &= ~0x03;
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outportl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
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if(read)
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x = inportl(PciDATA);
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else
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outportl(PciDATA, data);
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outportl(PciADDR, 0);
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break;
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case 2:
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outportb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
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outportb(PciFORWARD, BUSBNO(tbdf));
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if(read)
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x = inportl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
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else
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outportl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
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outportb(PciCSE, 0);
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break;
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}
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return x;
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}
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int
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pcicfgr32(Pcidev* pcidev, int rno)
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{
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return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
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}
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void
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pcicfgw32(Pcidev* pcidev, int rno, int data)
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{
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pcicfgrw32(pcidev->tbdf, rno, data, 0);
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}
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Pcidev*
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pcimatch(Pcidev* prev, int vid, int did)
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{
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if(pcicfgmode == -1)
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pcicfginit();
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if(prev == nil)
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prev = pcilist;
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else
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prev = prev->list;
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while(prev != nil) {
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if(prev->vid == vid && (did == 0 || prev->did == did))
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break;
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prev = prev->list;
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}
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return prev;
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}
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void
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pcihinv(Pcidev* p)
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{
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int i;
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Pcidev *t;
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if(pcicfgmode == -1)
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pcicfginit();
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if(p == nil) {
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p = pciroot;
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Bprint(&stdout, "bus dev type vid did intl memory\n");
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}
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for(t = p; t != nil; t = t->link) {
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Bprint(&stdout, "%d %2d/%d %.4ux %.4ux %.4ux %2d ",
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BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
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t->ccru, t->vid, t->did, t->intl);
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for(i = 0; i < nelem(p->mem); i++) {
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if(t->mem[i].size == 0)
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continue;
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Bprint(&stdout, "%d:%.8lux %d ", i,
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t->mem[i].bar, t->mem[i].size);
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}
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Bprint(&stdout, "\n");
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}
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while(p != nil) {
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if(p->bridge != nil)
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pcihinv(p->bridge);
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p = p->link;
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}
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}
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