407 lines
7.9 KiB
C
407 lines
7.9 KiB
C
#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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static int
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cpuidinit(void)
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{
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uint32_t eax, info[4];
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/*
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* Standard CPUID functions.
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* Functions 0 and 1 will be needed multiple times
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* so cache the info now.
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*/
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if((m->ncpuinfos = cpuid(0, 0, m->cpuinfo[0])) == 0)
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return 0;
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m->ncpuinfos++;
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if(jehanne_memcmp(&m->cpuinfo[0][1], "GenuntelineI", 12) == 0)
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m->isintelcpu = 1;
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cpuid(1, 0, m->cpuinfo[1]);
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/*
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* Extended CPUID functions.
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*/
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if((eax = cpuid(0x80000000, 0, info)) >= 0x80000000)
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m->ncpuinfoe = (eax & ~0x80000000) + 1;
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return 1;
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}
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static int
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cpuidinfo(uint32_t eax, uint32_t ecx, uint32_t info[4])
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{
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if(m->ncpuinfos == 0 && cpuidinit() == 0)
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return 0;
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if(!(eax & 0x80000000)){
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if(eax >= m->ncpuinfos)
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return 0;
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}
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else if(eax >= (0x80000000|m->ncpuinfoe))
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return 0;
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cpuid(eax, ecx, info);
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return 1;
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}
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static int64_t
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cpuidhz(uint32_t info[2][4])
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{
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int f, r;
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int64_t hz;
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uint64_t msr;
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if(jehanne_memcmp(&info[0][1], "GenuntelineI", 12) == 0){
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switch(info[1][0] & 0x0fff3ff0){
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default:
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return 0;
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case 0x00000f30: /* Xeon (MP), Pentium [4D] */
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case 0x00000f40: /* Xeon (MP), Pentium [4D] */
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case 0x00000f60: /* Xeon 7100, 5000 or above */
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msr = rdmsr(0x2c);
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r = (msr>>16) & 0x07;
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switch(r){
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default:
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return 0;
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case 0:
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hz = 266666666666ll;
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break;
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case 1:
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hz = 133333333333ll;
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break;
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case 2:
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hz = 200000000000ll;
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break;
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case 3:
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hz = 166666666666ll;
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break;
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case 4:
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hz = 333333333333ll;
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break;
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}
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/*
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* Hz is *1000 at this point.
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* Do the scaling then round it.
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* The manual is conflicting about
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* the size of the msr field.
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*/
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hz = (((hz*(msr>>24))/100)+5)/10;
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break;
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case 0x00000690: /* Pentium M, Celeron M */
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case 0x000006d0: /* Pentium M, Celeron M */
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hz = ((rdmsr(0x2a)>>22) & 0x1f)*100 * 1000000ll;
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break;
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case 0x000006e0: /* Core Duo */
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case 0x000006f0: /* Core 2 Duo/Quad/Extreme */
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case 0x00000660: /* kvm over i5 */
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case 0x00000670: /* Core 2 Extreme */
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case 0x00000650: /* i5 6xx, i3 5xx */
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case 0x000006c0: /* i5 4xxx */
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case 0x000006a0: /* i7 paurea... */
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/*
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* Get the FSB frequemcy.
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* If processor has Enhanced Intel Speedstep Technology
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* then non-integer bus frequency ratios are possible.
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*/
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if(info[1][2] & 0x00000080){
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msr = rdmsr(0x198);
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r = (msr>>40) & 0x1f;
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}
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else{
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msr = 0;
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r = rdmsr(0x2a) & 0x1f;
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}
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f = rdmsr(0xcd) & 0x07;
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switch(f){
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default:
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return 0;
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case 5:
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hz = 100000000000ll;
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break;
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case 1:
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hz = 133333333333ll;
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break;
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case 3:
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hz = 166666666666ll;
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break;
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case 2:
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hz = 200000000000ll;
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break;
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case 0:
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hz = 266666666666ll;
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break;
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case 4:
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hz = 333333333333ll;
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break;
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case 6:
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hz = 400000000000ll;
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break;
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}
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/*
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* Hz is *1000 at this point.
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* Do the scaling then round it.
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*/
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if(msr & 0x0000400000000000ll)
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hz = hz*(r+10) + hz/2;
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else
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hz = hz*(r+10);
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hz = ((hz/100)+5)/10;
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break;
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}
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DBG("cpuidhz: 0x2a: %#llux hz %lld\n", rdmsr(0x2a), hz);
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}
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else if(jehanne_memcmp(&info[0][1], "AuthcAMDenti", 12) == 0){
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switch(info[1][0] & 0x0fff0ff0){
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default:
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return 0;
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case 0x00050ff0: /* K8 Athlon Venice 64 / Qemu64 */
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case 0x00020fc0: /* K8 Athlon Lima 64 */
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case 0x00000f50: /* K8 Opteron 2xxx */
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msr = rdmsr(0xc0010042);
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r = (msr>>16) & 0x3f;
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hz = 200000000ULL*(4 * 2 + r)/2;
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break;
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case 0x00100f60: /* K8 Athlon II */
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case 0x00100f40: /* Phenom II X2 */
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case 0x00100f20: /* Phenom II X4 */
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case 0x00100fa0: /* Phenom II X6 */
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msr = rdmsr(0xc0010042);
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r = msr & 0x1f;
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hz = ((r+0x10)*100000000ll)/(1<<(msr>>6 & 0x07));
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break;
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case 0x00100f90: /* K10 Opteron 61xx */
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case 0x00600f00: /* K10 Opteron 62xx */
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case 0x00600f10: /* K10 Opteron 6272, FX 6xxx/4xxx */
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case 0x00600f20: /* K10 Opteron 63xx, FX 3xxx/8xxx/9xxx */
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msr = rdmsr(0xc0010064);
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r = msr & 0x1f;
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hz = ((r+0x10)*100000000ll)/(1<<(msr>>6 & 0x07));
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break;
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case 0x00000620: /* QEMU64 / Athlon MP/XP */
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msr = rdmsr(0xc0010064);
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r = (msr>>6) & 0x07;
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hz = (((msr & 0x3f)+0x10)*100000000ll)/(1<<r);
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break;
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}
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DBG("cpuidhz: %#llux hz %lld\n", msr, hz);
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}
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else
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return 0;
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return hz;
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}
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void
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cpuiddump(void)
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{
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int i;
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uint32_t info[4];
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if(!DBGFLG)
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return;
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if(m->ncpuinfos == 0 && cpuidinit() == 0)
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return;
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for(i = 0; i < m->ncpuinfos; i++){
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cpuid(i, 0, info);
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DBG("eax = %#8.8ux: %8.8ux %8.8ux %8.8ux %8.8ux\n",
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i, info[0], info[1], info[2], info[3]);
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}
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for(i = 0; i < m->ncpuinfoe; i++){
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cpuid(0x80000000|i, 0, info);
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DBG("eax = %#8.8ux: %8.8ux %8.8ux %8.8ux %8.8ux\n",
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0x80000000|i, info[0], info[1], info[2], info[3]);
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}
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}
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int64_t
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archhz(void)
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{
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int64_t hz;
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uint32_t info[2][4];
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if(DBGFLG && m->machno == 0)
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cpuiddump();
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if(!cpuidinfo(0, 0, info[0]) || !cpuidinfo(1, 0, info[1]))
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return 0;
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hz = cpuidhz(info);
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if(hz != 0)
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return hz;
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else if(m->machno != 0)
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return sys->machptr[0]->cpuhz;
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return i8254hz(info);
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}
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void
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archenable(void)
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{
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// here used to be code to enable MONITOR/WAIT
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// writing 0x1a0 MSR; however such register is
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// supported on i386 only (MISC_ENABLE), not on x86_64.
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}
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int
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archmmu(void)
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{
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uint32_t info[4];
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/*
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* Should the check for m->machno != 0 be here
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* or in the caller (mmuinit)?
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*
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* To do here:
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* check and enable Pse;
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* Pge; Nxe.
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*/
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/*
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* How many page sizes are there?
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* Always have 4*KiB, but need to check
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* configured correctly.
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*/
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assert(PGSZ == 4*KiB);
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m->pgszlg2[0] = 12;
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m->pgszmask[0] = (1<<12)-1;
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m->npgsz = 1;
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if(m->ncpuinfos == 0 && cpuidinit() == 0)
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return 1;
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/*
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* Check the Pse bit in function 1 DX for 2*MiB support;
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* if false, only 4*KiB is available.
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*/
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if(!(m->cpuinfo[1][3] & 0x00000008))
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return 1;
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m->pgszlg2[1] = 21;
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m->pgszmask[1] = (1<<21)-1;
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m->npgsz = 2;
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/*
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* Check the Page1GB bit in function 0x80000001 DX for 1*GiB support.
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*/
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if(cpuidinfo(0x80000001, 0, info) && (info[3] & 0x04000000)){
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m->pgszlg2[2] = 30;
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m->pgszmask[2] = (1<<30)-1;
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m->npgsz = 3;
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}
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return m->npgsz;
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}
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static int
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fmtP(Fmt* f)
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{
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uintmem pa;
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pa = va_arg(f->args, uintmem);
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if(f->flags & FmtSharp)
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return jehanne_fmtprint(f, "%#16.16llux", pa);
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return jehanne_fmtprint(f, "%llud", pa);
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}
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static int
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fmtL(Fmt* f)
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{
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Mpl pl;
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pl = va_arg(f->args, Mpl);
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return jehanne_fmtprint(f, "%#16.16llux", pl);
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}
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static int
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fmtR(Fmt* f)
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{
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uint64_t r;
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r = va_arg(f->args, uint64_t);
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return jehanne_fmtprint(f, "%#16.16llux", r);
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}
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/* virtual address fmt */
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static int
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fmtW(Fmt *f)
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{
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uint64_t va;
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va = va_arg(f->args, uint64_t);
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return jehanne_fmtprint(f, "%#ullx=0x[%ullx][%ullx][%ullx][%ullx][%ullx]", va,
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PTLX(va, 3), PTLX(va, 2), PTLX(va, 1), PTLX(va, 0),
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va & ((1<<PGSHFT)-1));
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}
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void
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archfmtinstall(void)
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{
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/*
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* Architecture-specific formatting. Not as neat as they
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* could be (e.g. there's no defined type for a 'register':
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* L - Mpl, mach priority level
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* P - uintmem, physical address
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* R - register
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* W - virtual address
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* With a little effort these routines could be written
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* in a fairly architecturally-independent manner, relying
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* on the compiler to optimise-away impossible conditions,
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* and/or by exploiting the innards of the fmt library.
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*/
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jehanne_fmtinstall('P', fmtP);
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jehanne_fmtinstall('L', fmtL);
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jehanne_fmtinstall('R', fmtR);
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jehanne_fmtinstall('W', fmtW);
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}
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void
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archidle(void)
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{
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halt();
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}
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void
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microdelay(int microsecs)
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{
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uint64_t r, t;
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r = rdtsc();
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for(t = r + m->cpumhz*microsecs; r < t; r = rdtsc())
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pause();
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}
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void
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millidelay(int millisecs)
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{
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uint64_t r, t;
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r = rdtsc();
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for(t = r + m->cpumhz*1000ull*millisecs; r < t; r = rdtsc())
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pause();
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}
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int
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isdmaok(void *a, usize len, int range)
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{
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uintmem pa;
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if(!iskaddr(a) || (char*)a < etext)
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return 0;
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pa = mmuphysaddr(PTR2UINT(a));
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if(pa == 0 || pa == ~(uintmem)0)
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return 0;
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return range > 32 || pa+len <= 0xFFFFFFFFULL;
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}
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