153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/*
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* ECHI portable hardware definitions
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*/
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typedef struct Ecapio Ecapio;
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typedef struct Edbgio Edbgio;
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#pragma incomplete Ecapio;
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#pragma incomplete Edbgio;
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/*
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* EHCI interface registers and bits
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*/
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enum
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{
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/* Ecapio->parms reg. */
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Cnports = 0xF, /* nport bits */
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Cdbgportshift = 20, /* debug port */
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Cdbgportmask = 0xF,
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/* Ecapio->capparms bits */
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C64 = 1<<0, /* 64-bits */
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Cpfl = 1<<1, /* program'ble frame list: can be <1024 */
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Casp = 1<<2, /* asynch. sched. park */
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Ceecpshift = 8, /* extended capabilities ptr. */
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Ceecpmask = (1<<8) - 1,
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Clegacy = 1, /* legacy support cap. id */
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CLbiossem = 2, /* legacy cap. bios sem. */
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CLossem = 3, /* legacy cap. os sem */
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CLcontrol = 4, /* legacy support control & status */
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/* typed links */
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Lterm = 1,
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Litd = 0<<1,
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Lqh = 1<<1,
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Lsitd = 2<<1,
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Lfstn = 3<<1, /* we don't use these */
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/* Cmd reg. */
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Cstop = 0x00000, /* stop running */
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Crun = 0x00001, /* start operation */
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Chcreset = 0x00002, /* host controller reset */
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Cflsmask = 0x0000C, /* frame list size bits */
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Cfls1024 = 0x00000, /* frame list size 1024 */
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Cfls512 = 0x00004, /* frame list size 512 frames */
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Cfls256 = 0x00008, /* frame list size 256 frames */
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Cpse = 0x00010, /* periodic sched. enable */
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Case = 0x00020, /* async sched. enable */
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Ciasync = 0x00040, /* interrupt on async advance doorbell */
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Citc1 = 0x10000, /* interrupt threshold ctl. 1 µframe */
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Citc4 = 0x40000, /* same. 2 µframes */
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/* ... */
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Citc8 = 0x80000, /* same. 8 µframes (can go up to 64) */
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/* interrupt threshold ctl. in µframes (1-32 in powers of 2) */
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Citcshift = 16,
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Citcmask = 0xff << Citcshift,
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/* Sts reg. */
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Sasyncss = 0x08000, /* aync schedule status */
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Speriodss = 0x04000, /* periodic schedule status */
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Srecl = 0x02000, /* reclamnation (empty async sched.) */
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Shalted = 0x01000, /* h.c. is halted */
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Sasync = 0x00020, /* interrupt on async advance */
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Sherr = 0x00010, /* host system error */
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Sfrroll = 0x00008, /* frame list roll over */
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Sportchg = 0x00004, /* port change detect */
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Serrintr = 0x00002, /* error interrupt */
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Sintr = 0x00001, /* interrupt */
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Sintrs = 0x0003F, /* interrupts status */
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/* Intr reg. */
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Iusb = 0x01, /* intr. on usb */
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Ierr = 0x02, /* intr. on usb error */
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Iportchg = 0x04, /* intr. on port change */
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Ifrroll = 0x08, /* intr. on frlist roll over */
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Ihcerr = 0x10, /* intr. on host error */
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Iasync = 0x20, /* intr. on async advance enable */
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Iall = 0x3F, /* all interrupts */
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/* Config reg. */
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Callmine = 1, /* route all ports to us */
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/* Portsc reg. */
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Pspresent = 0x00000001, /* device present */
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Psstatuschg = 0x00000002, /* Pspresent changed */
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Psenable = 0x00000004, /* device enabled */
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Pschange = 0x00000008, /* Psenable changed */
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Psresume = 0x00000040, /* resume detected */
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Pssuspend = 0x00000080, /* port suspended */
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Psreset = 0x00000100, /* port reset */
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Pspower = 0x00001000, /* port power on */
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Psowner = 0x00002000, /* port owned by companion */
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Pslinemask = 0x00000C00, /* line status bits */
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Pslow = 0x00000400, /* low speed device */
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/* Debug port csw reg. */
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Cowner = 0x40000000, /* port owned by ehci */
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Cenable = 0x10000000, /* debug port enabled */
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Cdone = 0x00010000, /* request is done */
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Cbusy = 0x00000400, /* port in use by a driver */
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Cerrmask= 0x00000380, /* error code bits */
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Chwerr = 0x00000100, /* hardware error */
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Cterr = 0x00000080, /* transaction error */
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Cfailed = 0x00000040, /* transaction did fail */
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Cgo = 0x00000020, /* execute the transaction */
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Cwrite = 0x00000010, /* request is a write */
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Clen = 0x0000000F, /* data len */
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/* Debug port pid reg. */
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Prpidshift = 16, /* received pid */
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Prpidmask = 0xFF,
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Pspidshift = 8, /* sent pid */
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Pspidmask = 0xFF,
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Ptokshift = 0, /* token pid */
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Ptokmask = 0xFF,
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Ptoggle = 0x00008800, /* to update toggles */
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Ptogglemask = 0x0000FF00,
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/* Debug port addr reg. */
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Adevshift = 8, /* device address */
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Adevmask = 0x7F,
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Aepshift = 0, /* endpoint number */
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Aepmask = 0xF,
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};
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/*
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* Capability registers (hw)
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*/
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struct Ecapio
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{
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uint32_t cap; /* 00 controller capability register */
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uint32_t parms; /* 04 structural parameters register */
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uint32_t capparms; /* 08 capability parameters */
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uint32_t portroute; /* 0c not on the CS5536 */
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};
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/*
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* Debug port registers (hw)
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*/
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struct Edbgio
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{
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uint32_t csw; /* control and status */
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uint32_t pid; /* USB pid */
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uint8_t data[8]; /* data buffer */
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uint32_t addr; /* device and endpoint addresses */
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};
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