262 lines
7.5 KiB
C
262 lines
7.5 KiB
C
/*
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* MultiProcessor Specification Version 1.[14].
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*/
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typedef struct { /* floating pointer */
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uint8_t signature[4]; /* "_MP_" */
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int32_t physaddr; /* physical address of MP configuration table */
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uint8_t length; /* 1 */
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uint8_t specrev; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t type; /* MP system configuration type */
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uint8_t imcrp;
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uint8_t reserved[3];
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} _MP_;
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#define _MP_sz (4+4+1+1+1+1+1+3)
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typedef struct { /* configuration table header */
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uint8_t signature[4]; /* "PCMP" */
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uint16_t length; /* total table length */
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uint8_t version; /* [14] */
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uint8_t checksum; /* all bytes must add up to 0 */
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uint8_t product[20]; /* product id */
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uint32_t oemtable; /* OEM table pointer */
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uint16_t oemlength; /* OEM table length */
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uint16_t entry; /* entry count */
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uint32_t lapicbase; /* address of local APIC */
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uint16_t xlength; /* extended table length */
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uint8_t xchecksum; /* extended table checksum */
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uint8_t reserved;
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} PCMP;
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#define PCMPsz (4+2+1+1+20+4+2+2+4+2+1+1)
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typedef struct { /* processor table entry */
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uint8_t type; /* entry type (0) */
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uint8_t apicno; /* local APIC id */
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uint8_t version; /* local APIC verison */
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uint8_t flags; /* CPU flags */
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uint8_t signature[4]; /* CPU signature */
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uint32_t feature; /* feature flags from CPUID instruction */
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uint8_t reserved[8];
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} PCMPprocessor;
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#define PCMPprocessorsz (1+1+1+1+4+4+8)
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typedef struct { /* bus table entry */
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uint8_t type; /* entry type (1) */
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uint8_t busno; /* bus id */
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char string[6]; /* bus type string */
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} PCMPbus;
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#define PCMPbussz (1+1+6)
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typedef struct { /* I/O APIC table entry */
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uint8_t type; /* entry type (2) */
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uint8_t apicno; /* I/O APIC id */
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uint8_t version; /* I/O APIC version */
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uint8_t flags; /* I/O APIC flags */
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uint32_t addr; /* I/O APIC address */
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} PCMPioapic;
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#define PCMPioapicsz (1+1+1+1+4)
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typedef struct { /* interrupt table entry */
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uint8_t type; /* entry type ([34]) */
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uint8_t intr; /* interrupt type */
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uint16_t flags; /* interrupt flag */
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uint8_t busno; /* source bus id */
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uint8_t irq; /* source bus irq */
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uint8_t apicno; /* destination APIC id */
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uint8_t intin; /* destination APIC [L]INTIN# */
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} PCMPintr;
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#define PCMPintrsz (1+1+2+1+1+1+1)
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typedef struct { /* system address space mapping entry */
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uint8_t type; /* entry type (128) */
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uint8_t length; /* of this entry (20) */
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uint8_t busno; /* bus id */
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uint8_t addrtype;
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uint32_t addrbase[2];
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uint32_t addrlength[2];
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} PCMPsasm;
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#define PCMPsasmsz (1+1+1+1+8+8)
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typedef struct { /* bus hierarchy descriptor entry */
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uint8_t type; /* entry type (129) */
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uint8_t length; /* of this entry (8) */
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uint8_t busno; /* bus id */
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uint8_t info; /* bus info */
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uint8_t parent; /* parent bus */
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uint8_t reserved[3];
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} PCMPhierarchy;
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#define PCMPhirarchysz (1+1+1+1+1+3)
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typedef struct { /* compatibility bus address space modifier entry */
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uint8_t type; /* entry type (130) */
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uint8_t length; /* of this entry (8) */
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uint8_t busno; /* bus id */
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uint8_t modifier; /* address modifier */
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uint32_t range; /* predefined range list */
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} PCMPcbasm;
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#define PCMPcbasmsz (1+1+1+1+4)
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enum { /* table entry types */
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PcmpPROCESSOR = 0x00, /* one entry per processor */
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PcmpBUS = 0x01, /* one entry per bus */
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PcmpIOAPIC = 0x02, /* one entry per I/O APIC */
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PcmpIOINTR = 0x03, /* one entry per bus interrupt source */
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PcmpLINTR = 0x04, /* one entry per system interrupt source */
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PcmpSASM = 0x80,
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PcmpHIERARCHY = 0x81,
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PcmpCBASM = 0x82,
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/* PCMPprocessor and PCMPioapic flags */
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PcmpEN = 0x01, /* enabled */
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PcmpBP = 0x02, /* bootstrap processor */
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/* PCMPiointr and PCMPlintr flags */
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PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */
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PcmpHIGH = 0x01, /* active high */
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PcmpLOW = 0x03, /* active low */
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PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */
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PcmpEDGE = 0x04, /* edge-triggered */
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PcmpLEVEL = 0x0C, /* level-triggered */
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/* PCMPiointr and PCMPlintr interrupt type */
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PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */
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PcmpNMI = 0x01, /* non-maskable interrupt */
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PcmpSMI = 0x02, /* system management interrupt */
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PcmpExtINT = 0x03, /* vectored interrupt from external PIC */
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/* PCMPsasm addrtype */
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PcmpIOADDR = 0x00, /* I/O address */
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PcmpMADDR = 0x01, /* memory address */
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PcmpPADDR = 0x02, /* prefetch address */
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/* PCMPhierarchy info */
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PcmpSD = 0x01, /* subtractive decode bus */
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/* PCMPcbasm modifier */
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PcmpPR = 0x01, /* predefined range list */
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};
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/*
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* Condensed form of the MP Configuration Table.
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* This is created during a single pass through the MP Configuration
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* table.
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*/
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typedef struct Aintr Aintr;
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typedef struct Bus Bus;
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typedef struct Apic Apic;
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typedef struct Bus {
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uint8_t type;
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uint8_t busno;
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uint8_t po;
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uint8_t el;
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Aintr* aintr; /* interrupts tied to this bus */
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Bus* next;
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} Bus;
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typedef struct Aintr {
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PCMPintr* intr;
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Apic* apic;
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Aintr* next;
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} Aintr;
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typedef struct Apic {
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int type;
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int apicno;
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uint32_t* addr; /* register base address */
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uint32_t paddr;
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int flags; /* PcmpBP|PcmpEN */
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Lock; /* I/O APIC: register access */
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int mre; /* I/O APIC: maximum redirection entry */
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int gsibase; /* I/O APIC: global system interrupt base (acpi) */
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int lintr[2]; /* Local APIC */
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int machno;
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int online;
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} Apic;
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enum {
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MaxAPICNO = 254, /* 255 is physical broadcast */
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};
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enum { /* I/O APIC registers */
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IoapicID = 0x00, /* ID */
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IoapicVER = 0x01, /* version */
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IoapicARB = 0x02, /* arbitration ID */
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IoapicRDT = 0x10, /* redirection table */
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};
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/*
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* Common bits for
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* I/O APIC Redirection Table Entry;
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* Local APIC Local Interrupt Vector Table;
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* Local APIC Inter-Processor Interrupt;
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* Local APIC Timer Vector Table.
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*/
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enum {
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ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */
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ApicLOWEST = 0x00000100, /* Lowest priority */
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ApicSMI = 0x00000200, /* System Management Interrupt */
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ApicRR = 0x00000300, /* Remote Read */
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ApicNMI = 0x00000400,
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ApicINIT = 0x00000500, /* INIT/RESET */
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ApicSTARTUP = 0x00000600, /* Startup IPI */
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ApicExtINT = 0x00000700,
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ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
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ApicLOGICAL = 0x00000800,
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ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */
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ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
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ApicLOW = 0x00002000,
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ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
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ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */
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ApicLEVEL = 0x00008000,
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ApicIMASK = 0x00010000, /* [16] Interrupt Mask */
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};
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extern void ioapicinit(Apic*, int);
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extern void ioapicrdtr(Apic*, int, int*, int*);
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extern void ioapicrdtw(Apic*, int, int, int);
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extern void lapicclock(Ureg*, void*);
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extern int lapiceoi(int);
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extern void lapicerror(Ureg*, void*);
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extern void lapicicrw(uint32_t, uint32_t);
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extern void lapicinit(Apic*);
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extern void lapicintroff(void);
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extern void lapicintron(void);
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extern int lapicisr(int);
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extern void lapicnmidisable(void);
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extern void lapicnmienable(void);
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extern void lapiconline(void);
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extern void lapicspurious(Ureg*, void*);
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extern void lapicstartap(Apic*, uintptr_t);
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extern void lapictimerset(uint64_t);
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extern int mpintrinit(Bus*, PCMPintr*, int, int);
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extern void mpinit(void);
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extern int mpintrenable(Vctl*);
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extern void mpshutdown(void);
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extern void mpstartap(Apic*);
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extern Bus* mpbus;
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extern Bus* mpbuslast;
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extern int mpisabus;
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extern int mpeisabus;
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extern Apic *mpioapic[];
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extern Apic *mpapic[];
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