2049 lines
46 KiB
C
2049 lines
46 KiB
C
/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://git.9front.org/plan9front/plan9front/HEAD/info.html for a list of authors.
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*/
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/*
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* Intel 8254[340]NN Gigabit Ethernet PCI Controllers
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* as found on the Intel PRO/1000 series of adapters:
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* 82543GC Intel PRO/1000 T
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* 82544EI Intel PRO/1000 XT
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* 82540EM Intel PRO/1000 MT
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* 82541[GP]I
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* 82547GI
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* 82546GB
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* 82546EB
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* To Do:
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* finish autonegotiation code;
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* integrate fiber stuff back in (this ONLY handles
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* the CAT5 cards at the moment);
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* add checksum-offload;
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* add tuning control via ctl file;
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* this driver is little-endian specific.
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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#include "etherif.h"
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#include "ethermii.h"
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enum {
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i82542 = (0x1000<<16)|0x8086,
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i82543gc = (0x1004<<16)|0x8086,
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i82544ei = (0x1008<<16)|0x8086,
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i82544eif = (0x1009<<16)|0x8086,
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i82544gc = (0x100d<<16)|0x8086,
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i82540em = (0x100E<<16)|0x8086,
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i82540eplp = (0x101E<<16)|0x8086,
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i82545em = (0x100F<<16)|0x8086,
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i82545gmc = (0x1026<<16)|0x8086,
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i82547ei = (0x1019<<16)|0x8086,
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i82547gi = (0x1075<<16)|0x8086,
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i82541ei = (0x1013<<16)|0x8086,
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i82541gi = (0x1076<<16)|0x8086,
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i82541gi2 = (0x1077<<16)|0x8086,
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i82541pi = (0x107c<<16)|0x8086,
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i82546gb = (0x1079<<16)|0x8086,
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i82546eb = (0x1010<<16)|0x8086,
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};
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enum {
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Ctrl = 0x00000000, /* Device Control */
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Ctrldup = 0x00000004, /* Device Control Duplicate */
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Status = 0x00000008, /* Device Status */
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Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
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Ctrlext = 0x00000018, /* Extended Device Control */
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Mdic = 0x00000020, /* MDI Control */
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Fcal = 0x00000028, /* Flow Control Address Low */
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Fcah = 0x0000002C, /* Flow Control Address High */
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Fct = 0x00000030, /* Flow Control Type */
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Icr = 0x000000C0, /* Interrupt Cause Read */
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Ics = 0x000000C8, /* Interrupt Cause Set */
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Ims = 0x000000D0, /* Interrupt Mask Set/Read */
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Imc = 0x000000D8, /* Interrupt mask Clear */
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Rctl = 0x00000100, /* Receive Control */
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Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
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Txcw = 0x00000178, /* Transmit Configuration Word */
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Rxcw = 0x00000180, /* Receive Configuration Word */
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/* on the oldest cards (8254[23]), the Mta register is at 0x200 */
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Tctl = 0x00000400, /* Transmit Control */
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Tipg = 0x00000410, /* Transmit IPG */
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Tbt = 0x00000448, /* Transmit Burst Timer */
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Ait = 0x00000458, /* Adaptive IFS Throttle */
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Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
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Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
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Rdfh = 0x00002410, /* Receive data fifo head */
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Rdft = 0x00002418, /* Receive data fifo tail */
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Rdfhs = 0x00002420, /* Receive data fifo head saved */
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Rdfts = 0x00002428, /* Receive data fifo tail saved */
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Rdfpc = 0x00002430, /* Receive data fifo packet count */
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Rdbal = 0x00002800, /* Rd Base Address Low */
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Rdbah = 0x00002804, /* Rd Base Address High */
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Rdlen = 0x00002808, /* Receive Descriptor Length */
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Rdh = 0x00002810, /* Receive Descriptor Head */
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Rdt = 0x00002818, /* Receive Descriptor Tail */
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Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
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Rxdctl = 0x00002828, /* Receive Descriptor Control */
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Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
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Txdmac = 0x00003000, /* Transfer DMA Control */
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Ett = 0x00003008, /* Early Transmit Control */
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Tdfh = 0x00003410, /* Transmit data fifo head */
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Tdft = 0x00003418, /* Transmit data fifo tail */
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Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */
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Tdfts = 0x00003428, /* Transmit data fifo tail saved */
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Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */
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Tdbal = 0x00003800, /* Td Base Address Low */
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Tdbah = 0x00003804, /* Td Base Address High */
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Tdlen = 0x00003808, /* Transmit Descriptor Length */
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Tdh = 0x00003810, /* Transmit Descriptor Head */
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Tdt = 0x00003818, /* Transmit Descriptor Tail */
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Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
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Txdctl = 0x00003828, /* Transmit Descriptor Control */
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Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
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Statistics = 0x00004000, /* Start of Statistics Area */
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Gorcl = 0x88/4, /* Good Octets Received Count */
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Gotcl = 0x90/4, /* Good Octets Transmitted Count */
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Torl = 0xC0/4, /* Total Octets Received */
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Totl = 0xC8/4, /* Total Octets Transmitted */
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Nstatistics = 64,
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Rxcsum = 0x00005000, /* Receive Checksum Control */
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Mta = 0x00005200, /* Multicast Table Array */
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Ral = 0x00005400, /* Receive Address Low */
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Rah = 0x00005404, /* Receive Address High */
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Manc = 0x00005820, /* Management Control */
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};
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enum { /* Ctrl */
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Bem = 0x00000002, /* Big Endian Mode */
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Prior = 0x00000004, /* Priority on the PCI bus */
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Lrst = 0x00000008, /* Link Reset */
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Asde = 0x00000020, /* Auto-Speed Detection Enable */
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Slu = 0x00000040, /* Set Link Up */
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Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
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SspeedMASK = 0x00000300, /* Speed Selection */
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SspeedSHIFT = 8,
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Sspeed10 = 0x00000000, /* 10Mb/s */
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Sspeed100 = 0x00000100, /* 100Mb/s */
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Sspeed1000 = 0x00000200, /* 1000Mb/s */
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Frcspd = 0x00000800, /* Force Speed */
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Frcdplx = 0x00001000, /* Force Duplex */
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SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
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SwdpinsloSHIFT = 18,
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SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
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SwdpioloSHIFT = 22,
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Devrst = 0x04000000, /* Device Reset */
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Rfce = 0x08000000, /* Receive Flow Control Enable */
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Tfce = 0x10000000, /* Transmit Flow Control Enable */
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Vme = 0x40000000, /* VLAN Mode Enable */
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};
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/*
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* can't find Tckok nor Rbcok in any Intel docs,
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* but even 82543gc docs define Lanid.
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*/
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enum { /* Status */
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Lu = 0x00000002, /* Link Up */
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Lanid = 0x0000000C, /* mask for Lan ID. (function id) */
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// Tckok = 0x00000004, /* Transmit clock is running */
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// Rbcok = 0x00000008, /* Receive clock is running */
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Txoff = 0x00000010, /* Transmission Paused */
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Tbimode = 0x00000020, /* TBI Mode Indication */
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LspeedMASK = 0x000000C0, /* Link Speed Setting */
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LspeedSHIFT = 6,
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Lspeed10 = 0x00000000, /* 10Mb/s */
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Lspeed100 = 0x00000040, /* 100Mb/s */
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Lspeed1000 = 0x00000080, /* 1000Mb/s */
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Mtxckok = 0x00000400, /* MTX clock is running */
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Pci66 = 0x00000800, /* PCI Bus speed indication */
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Bus64 = 0x00001000, /* PCI Bus width indication */
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Pcixmode = 0x00002000, /* PCI-X mode */
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PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */
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PcixspeedSHIFT = 14,
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Pcix66 = 0x00000000, /* 50-66MHz */
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Pcix100 = 0x00004000, /* 66-100MHz */
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Pcix133 = 0x00008000, /* 100-133MHz */
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};
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enum { /* Ctrl and Status */
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Fd = 0x00000001, /* Full-Duplex */
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AsdvMASK = 0x00000300,
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AsdvSHIFT = 8,
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Asdv10 = 0x00000000, /* 10Mb/s */
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Asdv100 = 0x00000100, /* 100Mb/s */
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Asdv1000 = 0x00000200, /* 1000Mb/s */
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};
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enum { /* Eecd */
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Sk = 0x00000001, /* Clock input to the EEPROM */
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Cs = 0x00000002, /* Chip Select */
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Di = 0x00000004, /* Data Input to the EEPROM */
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Do = 0x00000008, /* Data Output from the EEPROM */
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Areq = 0x00000040, /* EEPROM Access Request */
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Agnt = 0x00000080, /* EEPROM Access Grant */
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Eepresent = 0x00000100, /* EEPROM Present */
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Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
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Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
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Spi = 0x00002000, /* EEPROM is SPI not Microwire */
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};
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enum { /* Ctrlext */
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Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
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SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
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SwdpinshiSHIFT = 4,
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SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
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SwdpiohiSHIFT = 8,
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Asdchk = 0x00001000, /* ASD Check */
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Eerst = 0x00002000, /* EEPROM Reset */
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Ips = 0x00004000, /* Invert Power State */
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Spdbyps = 0x00008000, /* Speed Select Bypass */
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};
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enum { /* EEPROM content offsets */
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Ea = 0x00, /* Ethernet Address */
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Cf = 0x03, /* Compatibility Field */
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Pba = 0x08, /* Printed Board Assembly number */
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Icw1 = 0x0A, /* Initialization Control Word 1 */
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Sid = 0x0B, /* Subsystem ID */
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Svid = 0x0C, /* Subsystem Vendor ID */
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Did = 0x0D, /* Device ID */
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Vid = 0x0E, /* Vendor ID */
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Icw2 = 0x0F, /* Initialization Control Word 2 */
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};
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enum { /* Mdic */
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MDIdMASK = 0x0000FFFF, /* Data */
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MDIdSHIFT = 0,
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MDIrMASK = 0x001F0000, /* PHY Register Address */
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MDIrSHIFT = 16,
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MDIpMASK = 0x03E00000, /* PHY Address */
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MDIpSHIFT = 21,
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MDIwop = 0x04000000, /* Write Operation */
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MDIrop = 0x08000000, /* Read Operation */
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MDIready = 0x10000000, /* End of Transaction */
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MDIie = 0x20000000, /* Interrupt Enable */
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MDIe = 0x40000000, /* Error */
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};
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enum { /* Icr, Ics, Ims, Imc */
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Txdw = 0x00000001, /* Transmit Descriptor Written Back */
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Txqe = 0x00000002, /* Transmit Queue Empty */
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Lsc = 0x00000004, /* Link Status Change */
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Rxseq = 0x00000008, /* Receive Sequence Error */
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Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */
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Rxo = 0x00000040, /* Receiver Overrun */
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Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
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Mdac = 0x00000200, /* MDIO Access Completed */
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Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
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Gpi0 = 0x00000800, /* General Purpose Interrupts */
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Gpi1 = 0x00001000,
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Gpi2 = 0x00002000,
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Gpi3 = 0x00004000,
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};
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/*
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* The Mdic register isn't implemented on the 82543GC,
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* the software defined pins are used instead.
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* These definitions work for the Intel PRO/1000 T Server Adapter.
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* The direction pin bits are read from the EEPROM.
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*/
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enum {
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Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
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Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
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Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
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Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
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Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
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Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
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};
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enum { /* Txcw */
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TxcwFd = 0x00000020, /* Full Duplex */
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TxcwHd = 0x00000040, /* Half Duplex */
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TxcwPauseMASK = 0x00000180, /* Pause */
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TxcwPauseSHIFT = 7,
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TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
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TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
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TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
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TxcwRfiSHIFT = 12,
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TxcwNpr = 0x00008000, /* Next Page Request */
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TxcwConfig = 0x40000000, /* Transmit COnfig Control */
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TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
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};
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enum { /* Rxcw */
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Rxword = 0x0000FFFF, /* Data from auto-negotiation process */
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Rxnocarrier = 0x04000000, /* Carrier Sense indication */
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Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */
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Rxchange = 0x10000000, /* Change to the Rxword indication */
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Rxconfig = 0x20000000, /* /C/ order set reception indication */
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Rxsync = 0x40000000, /* Lost bit synchronization indication */
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Anc = 0x80000000, /* Auto Negotiation Complete */
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};
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enum { /* Rctl */
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Rrst = 0x00000001, /* Receiver Software Reset */
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Ren = 0x00000002, /* Receiver Enable */
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Sbp = 0x00000004, /* Store Bad Packets */
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Upe = 0x00000008, /* Unicast Promiscuous Enable */
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Mpe = 0x00000010, /* Multicast Promiscuous Enable */
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Lpe = 0x00000020, /* Long Packet Reception Enable */
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LbmMASK = 0x000000C0, /* Loopback Mode */
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LbmOFF = 0x00000000, /* No Loopback */
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LbmTBI = 0x00000040, /* TBI Loopback */
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LbmMII = 0x00000080, /* GMII/MII Loopback */
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LbmXCVR = 0x000000C0, /* Transceiver Loopback */
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RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */
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RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
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RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
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RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
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MoMASK = 0x00003000, /* Multicast Offset */
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Mo47b36 = 0x00000000, /* bits [47:36] of received address */
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Mo46b35 = 0x00001000, /* bits [46:35] of received address */
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Mo45b34 = 0x00002000, /* bits [45:34] of received address */
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Mo43b32 = 0x00003000, /* bits [43:32] of received address */
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Bam = 0x00008000, /* Broadcast Accept Mode */
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BsizeMASK = 0x00030000, /* Receive Buffer Size */
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Bsize2048 = 0x00000000, /* Bsex = 0 */
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Bsize1024 = 0x00010000, /* Bsex = 0 */
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Bsize512 = 0x00020000, /* Bsex = 0 */
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Bsize256 = 0x00030000, /* Bsex = 0 */
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Bsize16384 = 0x00010000, /* Bsex = 1 */
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Vfe = 0x00040000, /* VLAN Filter Enable */
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Cfien = 0x00080000, /* Canonical Form Indicator Enable */
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Cfi = 0x00100000, /* Canonical Form Indicator value */
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Dpf = 0x00400000, /* Discard Pause Frames */
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Pmcf = 0x00800000, /* Pass MAC Control Frames */
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Bsex = 0x02000000, /* Buffer Size Extension */
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Secrc = 0x04000000, /* Strip CRC from incoming packet */
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};
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enum { /* Tctl */
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Trst = 0x00000001, /* Transmitter Software Reset */
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Ten = 0x00000002, /* Transmit Enable */
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Psp = 0x00000008, /* Pad Short Packets */
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CtMASK = 0x00000FF0, /* Collision Threshold */
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CtSHIFT = 4,
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ColdMASK = 0x003FF000, /* Collision Distance */
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ColdSHIFT = 12,
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Swxoff = 0x00400000, /* Sofware XOFF Transmission */
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Pbe = 0x00800000, /* Packet Burst Enable */
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Rtlc = 0x01000000, /* Re-transmit on Late Collision */
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Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
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};
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enum { /* [RT]xdctl */
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PthreshMASK = 0x0000003F, /* Prefetch Threshold */
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PthreshSHIFT = 0,
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HthreshMASK = 0x00003F00, /* Host Threshold */
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HthreshSHIFT = 8,
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WthreshMASK = 0x003F0000, /* Writeback Threshold */
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WthreshSHIFT = 16,
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Gran = 0x01000000, /* Granularity */
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LthreshMASK = 0xFE000000, /* Low Threshold */
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LthreshSHIFT = 25,
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};
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enum { /* Rxcsum */
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PcssMASK = 0x000000FF, /* Packet Checksum Start */
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PcssSHIFT = 0,
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Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
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Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
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};
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enum { /* Manc */
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Arpen = 0x00002000, /* Enable ARP Request Filtering */
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};
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enum { /* Receive Delay Timer Ring */
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DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */
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DelaySHIFT = 0,
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Fpd = 0x80000000, /* Flush partial Descriptor Block */
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};
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typedef struct Rd { /* Receive Descriptor */
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uint32_t addr[2];
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uint16_t length;
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uint16_t checksum;
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uint8_t status;
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uint8_t errors;
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uint16_t special;
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} Rd;
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enum { /* Rd status */
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Rdd = 0x01, /* Descriptor Done */
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Reop = 0x02, /* End of Packet */
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Ixsm = 0x04, /* Ignore Checksum Indication */
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Vp = 0x08, /* Packet is 802.1Q (matched VET) */
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Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
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Ipcs = 0x40, /* IP Checksum Calculated on Packet */
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Pif = 0x80, /* Passed in-exact filter */
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};
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enum { /* Rd errors */
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Ce = 0x01, /* CRC Error or Alignment Error */
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Se = 0x02, /* Symbol Error */
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Seq = 0x04, /* Sequence Error */
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Cxe = 0x10, /* Carrier Extension Error */
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Tcpe = 0x20, /* TCP/UDP Checksum Error */
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Ipe = 0x40, /* IP Checksum Error */
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Rxe = 0x80, /* RX Data Error */
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};
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typedef struct Td Td;
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struct Td { /* Transmit Descriptor */
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union {
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uint32_t addr[2]; /* Data */
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struct { /* Context */
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uint8_t ipcss;
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uint8_t ipcso;
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uint16_t ipcse;
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uint8_t tucss;
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uint8_t tucso;
|
|
uint16_t tucse;
|
|
};
|
|
};
|
|
uint32_t control;
|
|
uint32_t status;
|
|
};
|
|
|
|
enum { /* Td control */
|
|
LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
|
|
LenSHIFT = 0,
|
|
DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
|
|
DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
|
|
PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
|
|
Teop = 0x01000000, /* End of Packet (DD) */
|
|
PtypeIP = 0x02000000, /* IP Packet Type (CD) */
|
|
Ifcs = 0x02000000, /* Insert FCS (DD) */
|
|
Tse = 0x04000000, /* TCP Segmentation Enable */
|
|
Rs = 0x08000000, /* Report Status */
|
|
Rps = 0x10000000, /* Report Status Sent */
|
|
Dext = 0x20000000, /* Descriptor Extension */
|
|
Vle = 0x40000000, /* VLAN Packet Enable */
|
|
Ide = 0x80000000, /* Interrupt Delay Enable */
|
|
};
|
|
|
|
enum { /* Td status */
|
|
Tdd = 0x00000001, /* Descriptor Done */
|
|
Ec = 0x00000002, /* Excess Collisions */
|
|
Lc = 0x00000004, /* Late Collision */
|
|
Tu = 0x00000008, /* Transmit Underrun */
|
|
Iixsm = 0x00000100, /* Insert IP Checksum */
|
|
Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */
|
|
HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */
|
|
HdrlenSHIFT = 8,
|
|
VlanMASK = 0x0FFF0000, /* VLAN Identifier */
|
|
VlanSHIFT = 16,
|
|
Tcfi = 0x10000000, /* Canonical Form Indicator */
|
|
PriMASK = 0xE0000000, /* User Priority */
|
|
PriSHIFT = 29,
|
|
MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */
|
|
MssSHIFT = 16,
|
|
};
|
|
|
|
enum {
|
|
Nrd = 256, /* multiple of 8 */
|
|
Ntd = 64, /* multiple of 8 */
|
|
Nrb = 1024, /* private receive buffers per Ctlr */
|
|
Rbsz = 2048,
|
|
};
|
|
|
|
typedef struct Ctlr Ctlr;
|
|
typedef struct Ctlr {
|
|
int port;
|
|
Pcidev* pcidev;
|
|
Ctlr* next;
|
|
Ether* edev;
|
|
int active;
|
|
int started;
|
|
int id;
|
|
int cls;
|
|
uint16_t eeprom[0x40];
|
|
|
|
QLock alock; /* attach */
|
|
void* alloc; /* receive/transmit descriptors */
|
|
int nrd;
|
|
int ntd;
|
|
|
|
int* nic;
|
|
Lock imlock;
|
|
int im; /* interrupt mask */
|
|
|
|
Mii* mii;
|
|
Rendez lrendez;
|
|
int lim;
|
|
|
|
int link;
|
|
|
|
QLock slock;
|
|
uint32_t statistics[Nstatistics];
|
|
uint32_t lsleep;
|
|
uint32_t lintr;
|
|
uint32_t rsleep;
|
|
uint32_t rintr;
|
|
uint32_t txdw;
|
|
uint32_t tintr;
|
|
uint32_t ixsm;
|
|
uint32_t ipcs;
|
|
uint32_t tcpcs;
|
|
|
|
uint8_t ra[Eaddrlen]; /* receive address */
|
|
uint32_t mta[128]; /* multicast table array */
|
|
|
|
Rendez rrendez;
|
|
int rim;
|
|
int rdfree;
|
|
Rd* rdba; /* receive descriptor base address */
|
|
Block** rb; /* receive buffers */
|
|
int rdh; /* receive descriptor head */
|
|
int rdt; /* receive descriptor tail */
|
|
int rdtr; /* receive delay timer ring value */
|
|
|
|
Lock tlock;
|
|
int tbusy;
|
|
int tdfree;
|
|
Td* tdba; /* transmit descriptor base address */
|
|
Block** tb; /* transmit buffers */
|
|
int tdh; /* transmit descriptor head */
|
|
int tdt; /* transmit descriptor tail */
|
|
|
|
int txcw;
|
|
int fcrtl;
|
|
int fcrth;
|
|
} Ctlr;
|
|
|
|
#define csr32r(c, r) (*((c)->nic+((r)/4)))
|
|
#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
|
|
|
|
static Ctlr* igbectlrhead;
|
|
static Ctlr* igbectlrtail;
|
|
|
|
static char* statistics[Nstatistics] = {
|
|
"CRC Error",
|
|
"Alignment Error",
|
|
"Symbol Error",
|
|
"RX Error",
|
|
"Missed Packets",
|
|
"Single Collision",
|
|
"Excessive Collisions",
|
|
"Multiple Collision",
|
|
"Late Collisions",
|
|
nil,
|
|
"Collision",
|
|
"Transmit Underrun",
|
|
"Defer",
|
|
"Transmit - No CRS",
|
|
"Sequence Error",
|
|
"Carrier Extension Error",
|
|
"Receive Error Length",
|
|
nil,
|
|
"XON Received",
|
|
"XON Transmitted",
|
|
"XOFF Received",
|
|
"XOFF Transmitted",
|
|
"FC Received Unsupported",
|
|
"Packets Received (64 Bytes)",
|
|
"Packets Received (65-127 Bytes)",
|
|
"Packets Received (128-255 Bytes)",
|
|
"Packets Received (256-511 Bytes)",
|
|
"Packets Received (512-1023 Bytes)",
|
|
"Packets Received (1024-1522 Bytes)",
|
|
"Good Packets Received",
|
|
"Broadcast Packets Received",
|
|
"Multicast Packets Received",
|
|
"Good Packets Transmitted",
|
|
nil,
|
|
"Good Octets Received",
|
|
nil,
|
|
"Good Octets Transmitted",
|
|
nil,
|
|
nil,
|
|
nil,
|
|
"Receive No Buffers",
|
|
"Receive Undersize",
|
|
"Receive Fragment",
|
|
"Receive Oversize",
|
|
"Receive Jabber",
|
|
nil,
|
|
nil,
|
|
nil,
|
|
"Total Octets Received",
|
|
nil,
|
|
"Total Octets Transmitted",
|
|
nil,
|
|
"Total Packets Received",
|
|
"Total Packets Transmitted",
|
|
"Packets Transmitted (64 Bytes)",
|
|
"Packets Transmitted (65-127 Bytes)",
|
|
"Packets Transmitted (128-255 Bytes)",
|
|
"Packets Transmitted (256-511 Bytes)",
|
|
"Packets Transmitted (512-1023 Bytes)",
|
|
"Packets Transmitted (1024-1522 Bytes)",
|
|
"Multicast Packets Transmitted",
|
|
"Broadcast Packets Transmitted",
|
|
"TCP Segmentation Context Transmitted",
|
|
"TCP Segmentation Context Fail",
|
|
};
|
|
|
|
static long
|
|
igbeifstat(Ether* edev, void* a, long n, uint32_t offset)
|
|
{
|
|
Ctlr *ctlr;
|
|
char *p, *s;
|
|
int i, l, r;
|
|
uint64_t tuvl, ruvl;
|
|
|
|
p = smalloc(READSTR);
|
|
l = 0;
|
|
ctlr = edev->ctlr;
|
|
qlock(&ctlr->slock);
|
|
for(i = 0; i < Nstatistics; i++){
|
|
r = csr32r(ctlr, Statistics+i*4);
|
|
if((s = statistics[i]) == nil)
|
|
continue;
|
|
switch(i){
|
|
case Gorcl:
|
|
case Gotcl:
|
|
case Torl:
|
|
case Totl:
|
|
ruvl = r;
|
|
ruvl += ((uint64_t)csr32r(ctlr, Statistics+(i+1)*4))<<32;
|
|
tuvl = ruvl;
|
|
tuvl += ctlr->statistics[i];
|
|
tuvl += ((uint64_t)ctlr->statistics[i+1])<<32;
|
|
if(tuvl == 0)
|
|
continue;
|
|
ctlr->statistics[i] = tuvl;
|
|
ctlr->statistics[i+1] = tuvl>>32;
|
|
l += jehanne_snprint(p+l, READSTR-l, "%s: %llud %llud\n",
|
|
s, tuvl, ruvl);
|
|
i++;
|
|
break;
|
|
|
|
default:
|
|
ctlr->statistics[i] += r;
|
|
if(ctlr->statistics[i] == 0)
|
|
continue;
|
|
l += jehanne_snprint(p+l, READSTR-l, "%s: %ud %ud\n",
|
|
s, ctlr->statistics[i], r);
|
|
break;
|
|
}
|
|
}
|
|
|
|
l += jehanne_snprint(p+l, READSTR-l, "lintr: %ud %ud\n",
|
|
ctlr->lintr, ctlr->lsleep);
|
|
l += jehanne_snprint(p+l, READSTR-l, "rintr: %ud %ud\n",
|
|
ctlr->rintr, ctlr->rsleep);
|
|
l += jehanne_snprint(p+l, READSTR-l, "tintr: %ud %ud\n",
|
|
ctlr->tintr, ctlr->txdw);
|
|
l += jehanne_snprint(p+l, READSTR-l, "ixcs: %ud %ud %ud\n",
|
|
ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
|
|
l += jehanne_snprint(p+l, READSTR-l, "rdtr: %ud\n", ctlr->rdtr);
|
|
l += jehanne_snprint(p+l, READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext));
|
|
|
|
l += jehanne_snprint(p+l, READSTR-l, "eeprom:");
|
|
for(i = 0; i < 0x40; i++){
|
|
if(i && ((i & 0x07) == 0))
|
|
l += jehanne_snprint(p+l, READSTR-l, "\n ");
|
|
l += jehanne_snprint(p+l, READSTR-l, " %4.4uX", ctlr->eeprom[i]);
|
|
}
|
|
l += jehanne_snprint(p+l, READSTR-l, "\n");
|
|
|
|
if(ctlr->mii != nil && ctlr->mii->curphy != nil){
|
|
l += jehanne_snprint(p+l, READSTR-l, "phy: ");
|
|
for(i = 0; i < NMiiPhyr; i++){
|
|
if(i && ((i & 0x07) == 0))
|
|
l += jehanne_snprint(p+l, READSTR-l, "\n ");
|
|
r = miimir(ctlr->mii, i);
|
|
l += jehanne_snprint(p+l, READSTR-l, " %4.4uX", r);
|
|
}
|
|
jehanne_snprint(p+l, READSTR-l, "\n");
|
|
}
|
|
n = readstr(offset, a, n, p);
|
|
jehanne_free(p);
|
|
qunlock(&ctlr->slock);
|
|
|
|
return n;
|
|
}
|
|
|
|
enum {
|
|
CMrdtr,
|
|
};
|
|
|
|
static Cmdtab igbectlmsg[] = {
|
|
CMrdtr, "rdtr", 2,
|
|
};
|
|
|
|
static long
|
|
igbectl(Ether* edev, void* buf, long n)
|
|
{
|
|
int v;
|
|
char *p;
|
|
Ctlr *ctlr;
|
|
Cmdbuf *cb;
|
|
Cmdtab *ct;
|
|
|
|
if((ctlr = edev->ctlr) == nil)
|
|
error(Enonexist);
|
|
|
|
cb = parsecmd(buf, n);
|
|
if(waserror()){
|
|
jehanne_free(cb);
|
|
nexterror();
|
|
}
|
|
|
|
ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg));
|
|
switch(ct->index){
|
|
case CMrdtr:
|
|
v = jehanne_strtol(cb->f[1], &p, 0);
|
|
if(v < 0 || p == cb->f[1] || v > 0xFFFF)
|
|
error(Ebadarg);
|
|
ctlr->rdtr = v;;
|
|
csr32w(ctlr, Rdtr, Fpd|v);
|
|
break;
|
|
}
|
|
jehanne_free(cb);
|
|
poperror();
|
|
|
|
return n;
|
|
}
|
|
|
|
static void
|
|
igbepromiscuous(void* arg, int on)
|
|
{
|
|
int rctl;
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
rctl = csr32r(ctlr, Rctl);
|
|
rctl &= ~MoMASK;
|
|
rctl |= Mo47b36;
|
|
if(on)
|
|
rctl |= Upe|Mpe;
|
|
else
|
|
rctl &= ~(Upe|Mpe);
|
|
csr32w(ctlr, Rctl, rctl|Mpe); /* temporarily keep Mpe on */
|
|
}
|
|
|
|
static void
|
|
igbemulticast(void* arg, uint8_t* addr, int add)
|
|
{
|
|
int bit, x;
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
x = addr[5]>>1;
|
|
bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
|
|
/*
|
|
* multiple ether addresses can hash to the same filter bit,
|
|
* so it's never safe to clear a filter bit.
|
|
* if we want to clear filter bits, we need to keep track of
|
|
* all the multicast addresses in use, clear all the filter bits,
|
|
* then set the ones corresponding to in-use addresses.
|
|
*/
|
|
if(add)
|
|
ctlr->mta[x] |= 1<<bit;
|
|
// else
|
|
// ctlr->mta[x] &= ~(1<<bit);
|
|
|
|
csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
|
|
}
|
|
|
|
static void
|
|
igbeim(Ctlr* ctlr, int im)
|
|
{
|
|
ilock(&ctlr->imlock);
|
|
ctlr->im |= im;
|
|
csr32w(ctlr, Ims, ctlr->im);
|
|
iunlock(&ctlr->imlock);
|
|
}
|
|
|
|
static int
|
|
igbelim(void* ctlr)
|
|
{
|
|
return ((Ctlr*)ctlr)->lim != 0;
|
|
}
|
|
|
|
static void
|
|
igbelproc(void* arg)
|
|
{
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
MiiPhy *phy;
|
|
int ctrl, r;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
while(waserror())
|
|
;
|
|
for(;;){
|
|
if(ctlr->mii == nil || ctlr->mii->curphy == nil)
|
|
continue;
|
|
|
|
/*
|
|
* To do:
|
|
* logic to manage status change,
|
|
* this is incomplete but should work
|
|
* one time to set up the hardware.
|
|
*
|
|
* MiiPhy.speed, etc. should be in Mii.
|
|
*/
|
|
if(miistatus(ctlr->mii) < 0)
|
|
//continue;
|
|
goto enable;
|
|
|
|
phy = ctlr->mii->curphy;
|
|
ctrl = csr32r(ctlr, Ctrl);
|
|
|
|
switch(ctlr->id){
|
|
case i82543gc:
|
|
case i82544ei:
|
|
case i82544eif:
|
|
default:
|
|
if(!(ctrl & Asde)){
|
|
ctrl &= ~(SspeedMASK|Ilos|Fd);
|
|
ctrl |= Frcdplx|Frcspd;
|
|
if(phy->speed == 1000)
|
|
ctrl |= Sspeed1000;
|
|
else if(phy->speed == 100)
|
|
ctrl |= Sspeed100;
|
|
if(phy->fd)
|
|
ctrl |= Fd;
|
|
}
|
|
break;
|
|
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82547gi:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Collision Distance.
|
|
*/
|
|
r = csr32r(ctlr, Tctl);
|
|
r &= ~ColdMASK;
|
|
if(phy->fd)
|
|
r |= 64<<ColdSHIFT;
|
|
else
|
|
r |= 512<<ColdSHIFT;
|
|
csr32w(ctlr, Tctl, r);
|
|
|
|
/*
|
|
* Flow control.
|
|
*/
|
|
if(phy->rfc)
|
|
ctrl |= Rfce;
|
|
if(phy->tfc)
|
|
ctrl |= Tfce;
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
|
|
enable:
|
|
ctlr->lim = 0;
|
|
igbeim(ctlr, Lsc);
|
|
|
|
ctlr->lsleep++;
|
|
sleep(&ctlr->lrendez, igbelim, ctlr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
igbetxinit(Ctlr* ctlr)
|
|
{
|
|
int i, r;
|
|
Block *bp;
|
|
|
|
csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));
|
|
switch(ctlr->id){
|
|
default:
|
|
r = 6;
|
|
break;
|
|
case i82543gc:
|
|
case i82544ei:
|
|
case i82544eif:
|
|
case i82544gc:
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82541ei:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
case i82547ei:
|
|
case i82547gi:
|
|
r = 8;
|
|
break;
|
|
}
|
|
csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
|
|
csr32w(ctlr, Ait, 0);
|
|
csr32w(ctlr, Txdmac, 0);
|
|
|
|
csr32w(ctlr, Tdbal, PCIWADDR32(ctlr->tdba));
|
|
csr32w(ctlr, Tdbah, 0);
|
|
csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td));
|
|
ctlr->tdh = PREV(0, ctlr->ntd);
|
|
csr32w(ctlr, Tdh, 0);
|
|
ctlr->tdt = 0;
|
|
csr32w(ctlr, Tdt, 0);
|
|
|
|
for(i = 0; i < ctlr->ntd; i++){
|
|
if((bp = ctlr->tb[i]) != nil){
|
|
ctlr->tb[i] = nil;
|
|
freeb(bp);
|
|
}
|
|
jehanne_memset(&ctlr->tdba[i], 0, sizeof(Td));
|
|
}
|
|
ctlr->tdfree = ctlr->ntd;
|
|
|
|
csr32w(ctlr, Tidv, 128);
|
|
r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
|
|
|
|
switch(ctlr->id){
|
|
default:
|
|
break;
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82547gi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
r = csr32r(ctlr, Txdctl);
|
|
r &= ~WthreshMASK;
|
|
r |= Gran|(4<<WthreshSHIFT);
|
|
|
|
csr32w(ctlr, Tadv, 64);
|
|
break;
|
|
}
|
|
|
|
csr32w(ctlr, Txdctl, r);
|
|
|
|
r = csr32r(ctlr, Tctl);
|
|
r |= Ten;
|
|
csr32w(ctlr, Tctl, r);
|
|
}
|
|
|
|
static void
|
|
igbetransmit(Ether* edev)
|
|
{
|
|
Td *td;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
int tdh, tdt;
|
|
|
|
ctlr = edev->ctlr;
|
|
|
|
ilock(&ctlr->tlock);
|
|
|
|
/*
|
|
* Free any completed packets
|
|
*/
|
|
tdh = ctlr->tdh;
|
|
while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){
|
|
if((bp = ctlr->tb[tdh]) != nil){
|
|
ctlr->tb[tdh] = nil;
|
|
freeb(bp);
|
|
}
|
|
jehanne_memset(&ctlr->tdba[tdh], 0, sizeof(Td));
|
|
tdh = NEXT(tdh, ctlr->ntd);
|
|
}
|
|
ctlr->tdh = tdh;
|
|
|
|
/*
|
|
* Try to fill the ring back up.
|
|
*/
|
|
tdt = ctlr->tdt;
|
|
while(NEXT(tdt, ctlr->ntd) != tdh){
|
|
if((bp = qget(edev->netif.oq)) == nil)
|
|
break;
|
|
td = &ctlr->tdba[tdt];
|
|
td->addr[0] = PCIWADDR32(bp->rp);
|
|
td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT);
|
|
td->control |= Dext|Ifcs|Teop|DtypeDD;
|
|
ctlr->tb[tdt] = bp;
|
|
tdt = NEXT(tdt, ctlr->ntd);
|
|
if(NEXT(tdt, ctlr->ntd) == tdh){
|
|
td->control |= Rs;
|
|
ctlr->txdw++;
|
|
ctlr->tdt = tdt;
|
|
csr32w(ctlr, Tdt, tdt);
|
|
igbeim(ctlr, Txdw);
|
|
break;
|
|
}
|
|
ctlr->tdt = tdt;
|
|
csr32w(ctlr, Tdt, tdt);
|
|
}
|
|
|
|
iunlock(&ctlr->tlock);
|
|
}
|
|
|
|
static void
|
|
igbereplenish(Ctlr* ctlr)
|
|
{
|
|
Rd *rd;
|
|
int rdt;
|
|
Block *bp;
|
|
|
|
rdt = ctlr->rdt;
|
|
while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
|
|
rd = &ctlr->rdba[rdt];
|
|
if(ctlr->rb[rdt] == nil){
|
|
bp = allocb(Rbsz);
|
|
bp->rp = bp->lim - Rbsz;
|
|
bp->wp = bp->rp;
|
|
ctlr->rb[rdt] = bp;
|
|
rd->addr[0] = PCIWADDR32(bp->rp);
|
|
rd->addr[1] = 0;
|
|
}
|
|
coherence();
|
|
rd->status = 0;
|
|
rdt = NEXT(rdt, ctlr->nrd);
|
|
ctlr->rdfree++;
|
|
}
|
|
ctlr->rdt = rdt;
|
|
csr32w(ctlr, Rdt, rdt);
|
|
}
|
|
|
|
static void
|
|
igberxinit(Ctlr* ctlr)
|
|
{
|
|
int i;
|
|
Block *bp;
|
|
|
|
/* temporarily keep Mpe on */
|
|
csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF|Mpe);
|
|
|
|
csr32w(ctlr, Rdbal, PCIWADDR32(ctlr->rdba));
|
|
csr32w(ctlr, Rdbah, 0);
|
|
csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd));
|
|
ctlr->rdh = 0;
|
|
csr32w(ctlr, Rdh, 0);
|
|
ctlr->rdt = 0;
|
|
csr32w(ctlr, Rdt, 0);
|
|
ctlr->rdtr = 0;
|
|
csr32w(ctlr, Rdtr, Fpd|0);
|
|
|
|
for(i = 0; i < ctlr->nrd; i++){
|
|
if((bp = ctlr->rb[i]) != nil){
|
|
ctlr->rb[i] = nil;
|
|
freeb(bp);
|
|
}
|
|
}
|
|
igbereplenish(ctlr);
|
|
|
|
switch(ctlr->id){
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
case i82547gi:
|
|
csr32w(ctlr, Radv, 64);
|
|
break;
|
|
}
|
|
csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
|
|
|
|
/*
|
|
* Disable checksum offload as it has known bugs.
|
|
*/
|
|
csr32w(ctlr, Rxcsum, ETHERHDRSIZE<<PcssSHIFT);
|
|
}
|
|
|
|
static int
|
|
igberim(void* ctlr)
|
|
{
|
|
return ((Ctlr*)ctlr)->rim != 0;
|
|
}
|
|
|
|
static void
|
|
igberproc(void* arg)
|
|
{
|
|
Rd *rd;
|
|
Block *bp;
|
|
Ctlr *ctlr;
|
|
int r, rdh;
|
|
Ether *edev;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
igberxinit(ctlr);
|
|
r = csr32r(ctlr, Rctl);
|
|
r |= Ren;
|
|
csr32w(ctlr, Rctl, r);
|
|
|
|
while(waserror())
|
|
;
|
|
|
|
for(;;){
|
|
ctlr->rim = 0;
|
|
igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
|
|
ctlr->rsleep++;
|
|
sleep(&ctlr->rrendez, igberim, ctlr);
|
|
|
|
rdh = ctlr->rdh;
|
|
for(;;){
|
|
rd = &ctlr->rdba[rdh];
|
|
|
|
if(!(rd->status & Rdd))
|
|
break;
|
|
|
|
/*
|
|
* Accept eop packets with no errors.
|
|
* With no errors and the Ixsm bit set,
|
|
* the descriptor status Tpcs and Ipcs bits give
|
|
* an indication of whether the checksums were
|
|
* calculated and valid.
|
|
*/
|
|
if((rd->status & Reop) && rd->errors == 0){
|
|
bp = ctlr->rb[rdh];
|
|
ctlr->rb[rdh] = nil;
|
|
bp->wp += rd->length;
|
|
bp->next = nil;
|
|
if(!(rd->status & Ixsm)){
|
|
ctlr->ixsm++;
|
|
if(rd->status & Ipcs){
|
|
/*
|
|
* IP checksum calculated
|
|
* (and valid as errors == 0).
|
|
*/
|
|
ctlr->ipcs++;
|
|
bp->flag |= Bipck;
|
|
}
|
|
if(rd->status & Tcpcs){
|
|
/*
|
|
* TCP/UDP checksum calculated
|
|
* (and valid as errors == 0).
|
|
*/
|
|
ctlr->tcpcs++;
|
|
bp->flag |= Btcpck|Budpck;
|
|
}
|
|
bp->checksum = rd->checksum;
|
|
bp->flag |= Bpktck;
|
|
}
|
|
etheriq(edev, bp, 1);
|
|
}
|
|
else if(ctlr->rb[rdh] != nil){
|
|
freeb(ctlr->rb[rdh]);
|
|
ctlr->rb[rdh] = nil;
|
|
}
|
|
|
|
jehanne_memset(rd, 0, sizeof(Rd));
|
|
coherence();
|
|
ctlr->rdfree--;
|
|
rdh = NEXT(rdh, ctlr->nrd);
|
|
}
|
|
ctlr->rdh = rdh;
|
|
|
|
if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
|
|
igbereplenish(ctlr);
|
|
}
|
|
}
|
|
|
|
static void
|
|
igbeattach(Ether* edev)
|
|
{
|
|
Ctlr *ctlr;
|
|
char name[KNAMELEN];
|
|
|
|
ctlr = edev->ctlr;
|
|
ctlr->edev = edev; /* point back to Ether* */
|
|
qlock(&ctlr->alock);
|
|
if(ctlr->alloc != nil){ /* already allocated? */
|
|
qunlock(&ctlr->alock);
|
|
return;
|
|
}
|
|
|
|
ctlr->nrd = ROUND(Nrd, 8);
|
|
ctlr->ntd = ROUND(Ntd, 8);
|
|
ctlr->alloc = jehanne_malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127);
|
|
if(ctlr->alloc == nil){
|
|
jehanne_print("igbe: can't allocate ctlr->alloc\n");
|
|
qunlock(&ctlr->alock);
|
|
return;
|
|
}
|
|
ctlr->rdba = (Rd*)ROUNDUP((uintptr_t)ctlr->alloc, 128);
|
|
ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd);
|
|
|
|
ctlr->rb = jehanne_malloc(ctlr->nrd*sizeof(Block*));
|
|
ctlr->tb = jehanne_malloc(ctlr->ntd*sizeof(Block*));
|
|
if (ctlr->rb == nil || ctlr->tb == nil) {
|
|
jehanne_print("igbe: can't allocate ctlr->rb or ctlr->tb\n");
|
|
qunlock(&ctlr->alock);
|
|
return;
|
|
}
|
|
|
|
if(waserror()){
|
|
jehanne_free(ctlr->tb);
|
|
ctlr->tb = nil;
|
|
jehanne_free(ctlr->rb);
|
|
ctlr->rb = nil;
|
|
jehanne_free(ctlr->alloc);
|
|
ctlr->alloc = nil;
|
|
qunlock(&ctlr->alock);
|
|
nexterror();
|
|
}
|
|
|
|
jehanne_snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
|
|
kproc(name, igbelproc, edev);
|
|
|
|
jehanne_snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
|
|
kproc(name, igberproc, edev);
|
|
|
|
igbetxinit(ctlr);
|
|
|
|
qunlock(&ctlr->alock);
|
|
poperror();
|
|
}
|
|
|
|
static void
|
|
igbeinterrupt(Ureg* _, void* arg)
|
|
{
|
|
Ctlr *ctlr;
|
|
Ether *edev;
|
|
int icr, im, txdw;
|
|
|
|
edev = arg;
|
|
ctlr = edev->ctlr;
|
|
|
|
ilock(&ctlr->imlock);
|
|
csr32w(ctlr, Imc, ~0);
|
|
im = ctlr->im;
|
|
txdw = 0;
|
|
|
|
while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
|
|
if(icr & Lsc){
|
|
im &= ~Lsc;
|
|
ctlr->lim = icr & Lsc;
|
|
wakeup(&ctlr->lrendez);
|
|
ctlr->lintr++;
|
|
}
|
|
if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){
|
|
im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq);
|
|
ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq);
|
|
wakeup(&ctlr->rrendez);
|
|
ctlr->rintr++;
|
|
}
|
|
if(icr & Txdw){
|
|
im &= ~Txdw;
|
|
txdw++;
|
|
ctlr->tintr++;
|
|
}
|
|
}
|
|
|
|
ctlr->im = im;
|
|
csr32w(ctlr, Ims, im);
|
|
iunlock(&ctlr->imlock);
|
|
|
|
if(txdw)
|
|
igbetransmit(edev);
|
|
}
|
|
|
|
static int
|
|
i82543mdior(Ctlr* ctlr, int n)
|
|
{
|
|
int ctrl, data, i, r;
|
|
|
|
/*
|
|
* Read n bits from the Management Data I/O Interface.
|
|
*/
|
|
ctrl = csr32r(ctlr, Ctrl);
|
|
r = (ctrl & ~Mddo)|Mdco;
|
|
data = 0;
|
|
for(i = n-1; i >= 0; i--){
|
|
if(csr32r(ctlr, Ctrl) & Mdd)
|
|
data |= (1<<i);
|
|
csr32w(ctlr, Ctrl, Mdc|r);
|
|
csr32w(ctlr, Ctrl, r);
|
|
}
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
|
|
return data;
|
|
}
|
|
|
|
static int
|
|
i82543mdiow(Ctlr* ctlr, int bits, int n)
|
|
{
|
|
int ctrl, i, r;
|
|
|
|
/*
|
|
* Write n bits to the Management Data I/O Interface.
|
|
*/
|
|
ctrl = csr32r(ctlr, Ctrl);
|
|
r = Mdco|Mddo|ctrl;
|
|
for(i = n-1; i >= 0; i--){
|
|
if(bits & (1<<i))
|
|
r |= Mdd;
|
|
else
|
|
r &= ~Mdd;
|
|
csr32w(ctlr, Ctrl, Mdc|r);
|
|
csr32w(ctlr, Ctrl, r);
|
|
}
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
i82543miimir(Mii* mii, int pa, int ra)
|
|
{
|
|
int data;
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
/*
|
|
* MII Management Interface Read.
|
|
*
|
|
* Preamble;
|
|
* ST+OP+PHYAD+REGAD;
|
|
* TA + 16 data bits.
|
|
*/
|
|
i82543mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
|
|
data = i82543mdior(ctlr, 18);
|
|
|
|
if(data & 0x10000)
|
|
return -1;
|
|
|
|
return data & 0xFFFF;
|
|
}
|
|
|
|
static int
|
|
i82543miimiw(Mii* mii, int pa, int ra, int data)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
/*
|
|
* MII Management Interface Write.
|
|
*
|
|
* Preamble;
|
|
* ST+OP+PHYAD+REGAD+TA + 16 data bits;
|
|
* Z.
|
|
*/
|
|
i82543mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
data &= 0xFFFF;
|
|
data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
|
|
i82543mdiow(ctlr, data, 32);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
igbemiimir(Mii* mii, int pa, int ra)
|
|
{
|
|
Ctlr *ctlr;
|
|
int mdic, timo;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
|
|
mdic = 0;
|
|
for(timo = 64; timo; timo--){
|
|
mdic = csr32r(ctlr, Mdic);
|
|
if(mdic & (MDIe|MDIready))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
|
|
if((mdic & (MDIe|MDIready)) == MDIready)
|
|
return mdic & 0xFFFF;
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
igbemiimiw(Mii* mii, int pa, int ra, int data)
|
|
{
|
|
Ctlr *ctlr;
|
|
int mdic, timo;
|
|
|
|
ctlr = mii->ctlr;
|
|
|
|
data &= MDIdMASK;
|
|
csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
|
|
mdic = 0;
|
|
for(timo = 64; timo; timo--){
|
|
mdic = csr32r(ctlr, Mdic);
|
|
if(mdic & (MDIe|MDIready))
|
|
break;
|
|
microdelay(1);
|
|
}
|
|
if((mdic & (MDIe|MDIready)) == MDIready)
|
|
return 0;
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
igbemii(Ctlr* ctlr)
|
|
{
|
|
MiiPhy *phy;
|
|
int ctrl, p, r;
|
|
|
|
r = csr32r(ctlr, Status);
|
|
if(r & Tbimode)
|
|
return -1;
|
|
if((ctlr->mii = jehanne_malloc(sizeof(Mii))) == nil)
|
|
return -1;
|
|
ctlr->mii->ctlr = ctlr;
|
|
|
|
ctrl = csr32r(ctlr, Ctrl);
|
|
ctrl |= Slu;
|
|
|
|
switch(ctlr->id){
|
|
case i82543gc:
|
|
ctrl |= Frcdplx|Frcspd;
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
|
|
/*
|
|
* The reset pin direction (Mdro) should already
|
|
* be set from the EEPROM load.
|
|
* If it's not set this configuration is unexpected
|
|
* so bail.
|
|
*/
|
|
r = csr32r(ctlr, Ctrlext);
|
|
if(!(r & Mdro)) {
|
|
jehanne_print("igbe: 82543gc Mdro not set\n");
|
|
return -1;
|
|
}
|
|
csr32w(ctlr, Ctrlext, r);
|
|
delay(20);
|
|
r = csr32r(ctlr, Ctrlext);
|
|
r &= ~Mdr;
|
|
csr32w(ctlr, Ctrlext, r);
|
|
delay(20);
|
|
r = csr32r(ctlr, Ctrlext);
|
|
r |= Mdr;
|
|
csr32w(ctlr, Ctrlext, r);
|
|
delay(20);
|
|
|
|
ctlr->mii->mir = i82543miimir;
|
|
ctlr->mii->miw = i82543miimiw;
|
|
break;
|
|
case i82544ei:
|
|
case i82544eif:
|
|
case i82544gc:
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82547ei:
|
|
case i82547gi:
|
|
case i82541ei:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
ctrl &= ~(Frcdplx|Frcspd);
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
ctlr->mii->mir = igbemiimir;
|
|
ctlr->mii->miw = igbemiimiw;
|
|
break;
|
|
default:
|
|
jehanne_free(ctlr->mii);
|
|
ctlr->mii = nil;
|
|
return -1;
|
|
}
|
|
|
|
if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
|
|
jehanne_free(ctlr->mii);
|
|
ctlr->mii = nil;
|
|
return -1;
|
|
}
|
|
USED(phy);
|
|
// jehanne_print("oui %X phyno %d\n", phy->oui, phy->phyno);
|
|
|
|
/*
|
|
* 8254X-specific PHY registers not in 802.3:
|
|
* 0x10 PHY specific control
|
|
* 0x14 extended PHY specific control
|
|
* Set appropriate values then reset the PHY to have
|
|
* changes noted.
|
|
*/
|
|
switch(ctlr->id){
|
|
case i82547gi:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
break;
|
|
default:
|
|
r = miimir(ctlr->mii, 16);
|
|
r |= 0x0800; /* assert CRS on Tx */
|
|
r |= 0x0060; /* auto-crossover all speeds */
|
|
r |= 0x0002; /* polarity reversal enabled */
|
|
miimiw(ctlr->mii, 16, r);
|
|
|
|
r = miimir(ctlr->mii, 20);
|
|
r |= 0x0070; /* +25MHz clock */
|
|
r &= ~0x0F00;
|
|
r |= 0x0100; /* 1x downshift */
|
|
miimiw(ctlr->mii, 20, r);
|
|
|
|
miireset(ctlr->mii);
|
|
p = 0;
|
|
if(ctlr->txcw & TxcwPs)
|
|
p |= AnaP;
|
|
if(ctlr->txcw & TxcwAs)
|
|
p |= AnaAP;
|
|
miiane(ctlr->mii, ~0, p, ~0);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
at93c46io(Ctlr* ctlr, char* op, int data)
|
|
{
|
|
char *lp, *p;
|
|
int i, loop, eecd, r;
|
|
|
|
eecd = csr32r(ctlr, Eecd);
|
|
|
|
r = 0;
|
|
loop = -1;
|
|
lp = nil;
|
|
for(p = op; *p != '\0'; p++){
|
|
switch(*p){
|
|
default:
|
|
return -1;
|
|
case ' ':
|
|
continue;
|
|
case ':': /* start of loop */
|
|
loop = jehanne_strtol(p+1, &lp, 0)-1;
|
|
lp--;
|
|
if(p == lp)
|
|
loop = 7;
|
|
p = lp;
|
|
continue;
|
|
case ';': /* end of loop */
|
|
if(lp == nil)
|
|
return -1;
|
|
loop--;
|
|
if(loop >= 0)
|
|
p = lp;
|
|
else
|
|
lp = nil;
|
|
continue;
|
|
case 'C': /* assert clock */
|
|
eecd |= Sk;
|
|
break;
|
|
case 'c': /* deassert clock */
|
|
eecd &= ~Sk;
|
|
break;
|
|
case 'D': /* next bit in 'data' byte */
|
|
if(loop < 0)
|
|
return -1;
|
|
if(data & (1<<loop))
|
|
eecd |= Di;
|
|
else
|
|
eecd &= ~Di;
|
|
break;
|
|
case 'O': /* collect data output */
|
|
i = (csr32r(ctlr, Eecd) & Do) != 0;
|
|
if(loop >= 0)
|
|
r |= (i<<loop);
|
|
else
|
|
r = i;
|
|
continue;
|
|
case 'H':
|
|
eecd |= Do;
|
|
continue;
|
|
case 'h':
|
|
eecd &= ~Do;
|
|
continue;
|
|
case 'I': /* assert data input */
|
|
eecd |= Di;
|
|
break;
|
|
case 'i': /* deassert data input */
|
|
eecd &= ~Di;
|
|
break;
|
|
case 'S': /* enable chip select */
|
|
eecd |= Cs;
|
|
break;
|
|
case 's': /* disable chip select */
|
|
eecd &= ~Cs;
|
|
break;
|
|
}
|
|
csr32w(ctlr, Eecd, eecd);
|
|
if (eecd & Spi)
|
|
microdelay(1);
|
|
else
|
|
microdelay(50);
|
|
}
|
|
if(loop >= 0)
|
|
return -1;
|
|
return r;
|
|
}
|
|
|
|
static int
|
|
at93c46r(Ctlr* ctlr)
|
|
{
|
|
uint16_t sum;
|
|
char rop[20];
|
|
int addr, areq, bits, data, eecd, i;
|
|
|
|
sum = 0;
|
|
eecd = csr32r(ctlr, Eecd);
|
|
|
|
switch(ctlr->id){
|
|
default:
|
|
areq = 0;
|
|
break;
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82541ei:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
case i82547ei:
|
|
case i82547gi:
|
|
areq = 1;
|
|
csr32w(ctlr, Eecd, eecd|Areq);
|
|
for(i = 0; i < 1000; i++){
|
|
if((eecd = csr32r(ctlr, Eecd)) & Agnt)
|
|
break;
|
|
microdelay(5);
|
|
}
|
|
if(!(eecd & Agnt)){
|
|
jehanne_print("igbe: not granted EEPROM access\n");
|
|
goto release;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if(eecd & Spi){
|
|
for(i = 0; i < 1000; i++){
|
|
at93c46io(ctlr, "H :8HDCc;", 0x05);
|
|
data = at93c46io(ctlr, "h :8COc;", 0);
|
|
|
|
if (!(data & 0x1))
|
|
break;
|
|
|
|
microdelay(5);
|
|
at93c46io(ctlr, "Ss", 0);
|
|
}
|
|
if(i == 1000){
|
|
jehanne_print("igbe: SPI EEPROM not ready\n");
|
|
goto release;
|
|
}
|
|
|
|
at93c46io(ctlr, "Ss H :8HDCc;", 0x03);
|
|
|
|
if(eecd & Eeszaddr)
|
|
bits = 16;
|
|
else
|
|
bits = 8;
|
|
jehanne_snprint(rop, sizeof(rop), "H :%dHDCc;", bits);
|
|
if(at93c46io(ctlr, rop, 0) != 0){
|
|
jehanne_print("igbe: can't set EEPROM address 0x00\n");
|
|
goto release;
|
|
}
|
|
|
|
for(addr = 0; addr < 0x40; addr++){
|
|
data = at93c46io(ctlr, "h :16COc;", 0);
|
|
ctlr->eeprom[addr] = (data >> 8) | (data << 8);
|
|
sum += ctlr->eeprom[addr];
|
|
}
|
|
} else {
|
|
if(eecd & (Eeszaddr|Eesz256))
|
|
bits = 8;
|
|
else
|
|
bits = 6;
|
|
jehanne_snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
|
|
|
|
for(addr = 0; addr < 0x40; addr++){
|
|
/*
|
|
* Read a word at address 'addr' from the Atmel AT93C46
|
|
* 3-Wire Serial EEPROM or compatible. The EEPROM access is
|
|
* controlled by 4 bits in Eecd. See the AT93C46 datasheet
|
|
* for protocol details.
|
|
*/
|
|
if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
|
|
jehanne_print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
|
|
goto release;
|
|
}
|
|
data = at93c46io(ctlr, ":16COc;", 0);
|
|
at93c46io(ctlr, "sic", 0);
|
|
ctlr->eeprom[addr] = data;
|
|
sum += data;
|
|
}
|
|
}
|
|
|
|
release:
|
|
if(areq)
|
|
csr32w(ctlr, Eecd, eecd & ~Areq);
|
|
return sum;
|
|
}
|
|
|
|
static int
|
|
igbedetach(Ctlr* ctlr)
|
|
{
|
|
int r, timeo;
|
|
|
|
/*
|
|
* Perform a device reset to get the chip back to the
|
|
* power-on state, followed by an EEPROM reset to read
|
|
* the defaults for some internal registers.
|
|
*/
|
|
csr32w(ctlr, Imc, ~0);
|
|
csr32w(ctlr, Rctl, 0);
|
|
csr32w(ctlr, Tctl, 0);
|
|
|
|
delay(10);
|
|
|
|
csr32w(ctlr, Ctrl, Devrst);
|
|
delay(1);
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr32r(ctlr, Ctrl) & Devrst))
|
|
break;
|
|
delay(1);
|
|
}
|
|
if(csr32r(ctlr, Ctrl) & Devrst)
|
|
return -1;
|
|
r = csr32r(ctlr, Ctrlext);
|
|
csr32w(ctlr, Ctrlext, r|Eerst);
|
|
delay(1);
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!(csr32r(ctlr, Ctrlext) & Eerst))
|
|
break;
|
|
delay(1);
|
|
}
|
|
if(csr32r(ctlr, Ctrlext) & Eerst)
|
|
return -1;
|
|
|
|
switch(ctlr->id){
|
|
default:
|
|
break;
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82547gi:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
r = csr32r(ctlr, Manc);
|
|
r &= ~Arpen;
|
|
csr32w(ctlr, Manc, r);
|
|
break;
|
|
}
|
|
|
|
csr32w(ctlr, Imc, ~0);
|
|
delay(1);
|
|
for(timeo = 0; timeo < 1000; timeo++){
|
|
if(!csr32r(ctlr, Icr))
|
|
break;
|
|
delay(1);
|
|
}
|
|
if(csr32r(ctlr, Icr))
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
igbeshutdown(Ether* ether)
|
|
{
|
|
igbedetach(ether->ctlr);
|
|
}
|
|
|
|
static int
|
|
igbereset(Ctlr* ctlr)
|
|
{
|
|
int ctrl, i, pause, r, swdpio, txcw;
|
|
|
|
if(igbedetach(ctlr))
|
|
return -1;
|
|
|
|
/*
|
|
* Read the EEPROM, validate the checksum
|
|
* then get the device back to a power-on state.
|
|
*/
|
|
if((r = at93c46r(ctlr)) != 0xBABA){
|
|
jehanne_print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Snarf and set up the receive addresses.
|
|
* There are 16 addresses. The first should be the MAC address.
|
|
* The others are cleared and not marked valid (MS bit of Rah).
|
|
*/
|
|
if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
|
|
BUSFNO(ctlr->pcidev->tbdf) == 1)
|
|
ctlr->eeprom[Ea+2] += 0x100; /* second interface */
|
|
if(ctlr->id == i82541gi && ctlr->eeprom[Ea] == 0xFFFF)
|
|
ctlr->eeprom[Ea] = 0xD000;
|
|
for(i = Ea; i < Eaddrlen/2; i++){
|
|
ctlr->ra[2*i] = ctlr->eeprom[i];
|
|
ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
|
|
}
|
|
/* lan id seems to vary on 82543gc; don't use it */
|
|
if (ctlr->id != i82543gc) {
|
|
r = (csr32r(ctlr, Status) & Lanid) >> 2;
|
|
ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */
|
|
}
|
|
|
|
r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
|
|
csr32w(ctlr, Ral, r);
|
|
r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
|
|
csr32w(ctlr, Rah, r);
|
|
for(i = 1; i < 16; i++){
|
|
csr32w(ctlr, Ral+i*8, 0);
|
|
csr32w(ctlr, Rah+i*8, 0);
|
|
}
|
|
|
|
/*
|
|
* Clear the Multicast Table Array.
|
|
* It's a 4096 bit vector accessed as 128 32-bit registers.
|
|
*/
|
|
jehanne_memset(ctlr->mta, 0, sizeof(ctlr->mta));
|
|
for(i = 0; i < 128; i++)
|
|
csr32w(ctlr, Mta+i*4, 0);
|
|
|
|
/*
|
|
* Just in case the Eerst didn't load the defaults
|
|
* (doesn't appear to fully on the 82543GC), do it manually.
|
|
*/
|
|
if (ctlr->id == i82543gc) {
|
|
txcw = csr32r(ctlr, Txcw);
|
|
txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
|
|
ctrl = csr32r(ctlr, Ctrl);
|
|
ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
|
|
|
|
if(ctlr->eeprom[Icw1] & 0x0400){
|
|
ctrl |= Fd;
|
|
txcw |= TxcwFd;
|
|
}
|
|
if(ctlr->eeprom[Icw1] & 0x0200)
|
|
ctrl |= Lrst;
|
|
if(ctlr->eeprom[Icw1] & 0x0010)
|
|
ctrl |= Ilos;
|
|
if(ctlr->eeprom[Icw1] & 0x0800)
|
|
ctrl |= Frcspd;
|
|
swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
|
|
ctrl |= swdpio<<SwdpioloSHIFT;
|
|
csr32w(ctlr, Ctrl, ctrl);
|
|
|
|
ctrl = csr32r(ctlr, Ctrlext);
|
|
ctrl &= ~(Ips|SwdpiohiMASK);
|
|
swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
|
|
if(ctlr->eeprom[Icw1] & 0x1000)
|
|
ctrl |= Ips;
|
|
ctrl |= swdpio<<SwdpiohiSHIFT;
|
|
csr32w(ctlr, Ctrlext, ctrl);
|
|
|
|
if(ctlr->eeprom[Icw2] & 0x0800)
|
|
txcw |= TxcwAne;
|
|
pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
|
|
txcw |= pause<<TxcwPauseSHIFT;
|
|
switch(pause){
|
|
default:
|
|
ctlr->fcrtl = 0x00002000;
|
|
ctlr->fcrth = 0x00004000;
|
|
txcw |= TxcwAs|TxcwPs;
|
|
break;
|
|
case 0:
|
|
ctlr->fcrtl = 0x00002000;
|
|
ctlr->fcrth = 0x00004000;
|
|
break;
|
|
case 2:
|
|
ctlr->fcrtl = 0;
|
|
ctlr->fcrth = 0;
|
|
txcw |= TxcwAs;
|
|
break;
|
|
}
|
|
ctlr->txcw = txcw;
|
|
csr32w(ctlr, Txcw, txcw);
|
|
}
|
|
|
|
|
|
/*
|
|
* Flow control - values from the datasheet.
|
|
*/
|
|
csr32w(ctlr, Fcal, 0x00C28001);
|
|
csr32w(ctlr, Fcah, 0x00000100);
|
|
csr32w(ctlr, Fct, 0x00008808);
|
|
csr32w(ctlr, Fcttv, 0x00000100);
|
|
|
|
csr32w(ctlr, Fcrtl, ctlr->fcrtl);
|
|
csr32w(ctlr, Fcrth, ctlr->fcrth);
|
|
|
|
if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
igbepci(void)
|
|
{
|
|
int cls;
|
|
Pcidev *p;
|
|
Ctlr *ctlr;
|
|
void *mem;
|
|
|
|
p = nil;
|
|
while(p = pcimatch(p, 0, 0)){
|
|
if(p->ccrb != 0x02 || p->ccru != 0)
|
|
continue;
|
|
|
|
switch((p->did<<16)|p->vid){
|
|
default:
|
|
continue;
|
|
case i82543gc:
|
|
case i82544ei:
|
|
case i82544eif:
|
|
case i82544gc:
|
|
case i82547ei:
|
|
case i82547gi:
|
|
case i82540em:
|
|
case i82540eplp:
|
|
case i82541ei:
|
|
case i82541gi:
|
|
case i82541gi2:
|
|
case i82541pi:
|
|
case i82545em:
|
|
case i82545gmc:
|
|
case i82546gb:
|
|
case i82546eb:
|
|
break;
|
|
}
|
|
|
|
mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
|
|
if(mem == nil){
|
|
jehanne_print("igbe: can't map %8.8luX\n", p->mem[0].bar);
|
|
continue;
|
|
}
|
|
cls = pcicfgr8(p, PciCLS);
|
|
switch(cls){
|
|
default:
|
|
jehanne_print("igbe: p->cls %#ux, setting to 0x10\n", p->cls);
|
|
p->cls = 0x10;
|
|
pcicfgw8(p, PciCLS, p->cls);
|
|
break;
|
|
case 0x08:
|
|
case 0x10:
|
|
break;
|
|
}
|
|
ctlr = jehanne_malloc(sizeof(Ctlr));
|
|
if(ctlr == nil){
|
|
jehanne_print("igbe: can't allocate memory\n");
|
|
continue;
|
|
}
|
|
ctlr->port = p->mem[0].bar & ~0x0F;
|
|
ctlr->pcidev = p;
|
|
ctlr->id = (p->did<<16)|p->vid;
|
|
ctlr->cls = cls*4;
|
|
ctlr->nic = mem;
|
|
|
|
if(igbereset(ctlr)){
|
|
jehanne_free(ctlr);
|
|
vunmap(mem, p->mem[0].size);
|
|
continue;
|
|
}
|
|
pcisetbme(p);
|
|
|
|
if(igbectlrhead != nil)
|
|
igbectlrtail->next = ctlr;
|
|
else
|
|
igbectlrhead = ctlr;
|
|
igbectlrtail = ctlr;
|
|
}
|
|
}
|
|
|
|
static int
|
|
igbepnp(Ether* edev)
|
|
{
|
|
Ctlr *ctlr;
|
|
|
|
if(igbectlrhead == nil)
|
|
igbepci();
|
|
|
|
/*
|
|
* Any adapter matches if no edev->port is supplied,
|
|
* otherwise the ports must match.
|
|
*/
|
|
for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
if(ctlr->active)
|
|
continue;
|
|
if(edev->port == 0 || edev->port == ctlr->port){
|
|
ctlr->active = 1;
|
|
break;
|
|
}
|
|
}
|
|
if(ctlr == nil)
|
|
return -1;
|
|
|
|
edev->ctlr = ctlr;
|
|
edev->port = ctlr->port;
|
|
edev->irq = ctlr->pcidev->intl;
|
|
edev->tbdf = ctlr->pcidev->tbdf;
|
|
edev->netif.mbps = 1000;
|
|
jehanne_memmove(edev->ea, ctlr->ra, Eaddrlen);
|
|
|
|
/*
|
|
* Linkage to the generic ethernet driver.
|
|
*/
|
|
edev->attach = igbeattach;
|
|
edev->transmit = igbetransmit;
|
|
edev->interrupt = igbeinterrupt;
|
|
edev->ifstat = igbeifstat;
|
|
edev->ctl = igbectl;
|
|
|
|
edev->netif.arg = edev;
|
|
edev->netif.promiscuous = igbepromiscuous;
|
|
edev->shutdown = igbeshutdown;
|
|
edev->netif.multicast = igbemulticast;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
etherigbelink(void)
|
|
{
|
|
addethercard("i82543", igbepnp);
|
|
addethercard("igbe", igbepnp);
|
|
}
|