301 lines
7.0 KiB
C
301 lines
7.0 KiB
C
/*
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* advanced host controller interface (sata)
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* © 2007 coraid, inc
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*/
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/* Copyright (C) Charles Forsyth
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* See /doc/license/NOTICE.Plan9-9k.txt for details about the licensing.
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*/
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/* Portions of this file are Copyright (C) 9front's team.
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* See /doc/license/9front-mit for details about the licensing.
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* See http://git.9front.org/plan9front/plan9front/HEAD/info.html for a list of authors.
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*/
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/* ata errors */
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enum {
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Emed = 1<<0, /* media error */
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Enm = 1<<1, /* no media */
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Eabrt = 1<<2, /* abort */
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Emcr = 1<<3, /* media change request */
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Eidnf = 1<<4, /* no user-accessible address */
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Emc = 1<<5, /* media change */
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Eunc = 1<<6, /* data error */
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Ewp = 1<<6, /* write protect */
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Eicrc = 1<<7, /* interface crc error */
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Efatal = Eidnf|Eicrc, /* must sw reset */
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};
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/* ata status */
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enum {
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ASerr = 1<<0, /* error */
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ASdrq = 1<<3, /* request */
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ASdf = 1<<5, /* fault */
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ASdrdy = 1<<6, /* ready */
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ASbsy = 1<<7, /* busy */
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ASobs = 1<<1|1<<2|1<<4,
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};
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/* pci configuration */
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enum {
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Abar = 5,
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};
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/*
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* ahci memory configuration
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*
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* 0000-0023 generic host control
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* 0024-009f reserved
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* 00a0-00ff vendor specific.
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* 0100-017f port 0
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* ...
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* 1080-1100 port 31
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*/
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/* cap bits: supported features */
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enum {
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Hs64a = 1<<31, /* 64-bit addressing */
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Hsncq = 1<<30, /* ncq */
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Hssntf = 1<<29, /* snotification reg. */
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Hsmps = 1<<28, /* mech pres switch */
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Hsss = 1<<27, /* staggered spinup */
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Hsalp = 1<<26, /* aggressive link pm */
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Hsal = 1<<25, /* activity led */
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Hsclo = 1<<24, /* command-list override */
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Hiss = 1<<20, /* for interface speed */
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// Hsnzo = 1<<19,
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Hsam = 1<<18, /* ahci-mode only */
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Hspm = 1<<17, /* port multiplier */
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// Hfbss = 1<<16,
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Hpmb = 1<<15, /* multiple-block pio */
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Hssc = 1<<14, /* slumber state */
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Hpsc = 1<<13, /* partial-slumber state */
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Hncs = 1<<8, /* n command slots */
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Hcccs = 1<<7, /* coal */
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Hems = 1<<6, /* enclosure mgmt. */
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Hsxs = 1<<5, /* external sata */
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Hnp = 1<<0, /* n ports */
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};
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/* ghc bits */
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enum {
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Hae = 1<<31, /* enable ahci */
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Hie = 1<<1, /* " interrupts */
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Hhr = 1<<0, /* hba reset */
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};
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typedef struct {
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uint32_t cap;
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uint32_t ghc;
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uint32_t isr;
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uint32_t pi; /* ports implemented */
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uint32_t ver;
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uint32_t ccc; /* coaleasing control */
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uint32_t cccports;
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uint32_t emloc;
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uint32_t emctl;
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} Ahba;
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enum {
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Acpds = 1<<31, /* cold port detect status */
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Atfes = 1<<30, /* task file error status */
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Ahbfs = 1<<29, /* hba fatal */
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Ahbds = 1<<28, /* hba error (parity error) */
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Aifs = 1<<27, /* interface fatal §6.1.2 */
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Ainfs = 1<<26, /* interface error (recovered) */
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Aofs = 1<<24, /* too many bytes from disk */
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Aipms = 1<<23, /* incorrect prt mul status */
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Aprcs = 1<<22, /* PhyRdy change status Pxserr.diag.n */
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Adpms = 1<<7, /* mechanical presence status */
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Apcs = 1<<6, /* port connect diag.x */
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Adps = 1<<5, /* descriptor processed */
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Aufs = 1<<4, /* unknown fis diag.f */
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Asdbs = 1<<3, /* set device bits fis received w/ i bit set */
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Adss = 1<<2, /* dma setup */
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Apio = 1<<1, /* pio setup fis */
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Adhrs = 1<<0, /* device to host register fis */
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IEM = Acpds|Atfes|Ahbds|Ahbfs|Ahbds|Aifs|Ainfs|Aprcs|Apcs|Adps|
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Aufs|Asdbs|Adss|Adhrs,
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Ifatal = Atfes|Ahbfs|Ahbds|Aifs,
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};
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/* serror bits */
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enum {
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SerrX = 1<<26, /* exchanged */
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SerrF = 1<<25, /* unknown fis */
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SerrT = 1<<24, /* transition error */
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SerrS = 1<<23, /* link sequence */
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SerrH = 1<<22, /* handshake */
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SerrC = 1<<21, /* crc */
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SerrD = 1<<20, /* not used by ahci */
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SerrB = 1<<19, /* 10-tp-8 decode */
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SerrW = 1<<18, /* comm wake */
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SerrI = 1<<17, /* phy internal */
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SerrN = 1<<16, /* phyrdy change */
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ErrE = 1<<11, /* internal */
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ErrP = 1<<10, /* ata protocol violation */
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ErrC = 1<<9, /* communication */
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ErrT = 1<<8, /* transient */
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ErrM = 1<<1, /* recoverd comm */
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ErrI = 1<<0, /* recovered data integrety */
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ErrAll = ErrE|ErrP|ErrC|ErrT|ErrM|ErrI,
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SerrAll = SerrX|SerrF|SerrT|SerrS|SerrH|SerrC|SerrD|SerrB|SerrW|
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SerrI|SerrN|ErrAll,
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SerrBad = 0x7f<<19,
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};
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/* cmd register bits */
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enum {
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Aicc = 1<<28, /* interface communcations control. 4 bits */
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Aasp = 1<<27, /* aggressive slumber & partial sleep */
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Aalpe = 1<<26, /* aggressive link pm enable */
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Adlae = 1<<25, /* drive led on atapi */
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Aatapi = 1<<24, /* device is atapi */
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Aesp = 1<<21, /* external sata port */
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Acpd = 1<<20, /* cold presence detect */
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Ampsp = 1<<19, /* mechanical pres. */
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Ahpcp = 1<<18, /* hot plug capable */
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Apma = 1<<17, /* pm attached */
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Acps = 1<<16, /* cold presence state */
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Acr = 1<<15, /* cmdlist running */
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Afr = 1<<14, /* fis running */
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Ampss = 1<<13, /* mechanical presence switch state */
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Accs = 1<<8, /* current command slot 12:08 */
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Afre = 1<<4, /* fis enable receive */
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Aclo = 1<<3, /* command list override */
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Apod = 1<<2, /* power on dev (requires cold-pres. detect) */
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Asud = 1<<1, /* spin-up device; requires ss capability */
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Ast = 1<<0, /* start */
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Arun = Ast|Acr|Afre|Afr,
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};
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/* ctl register bits */
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enum {
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Aipm = 1<<8, /* interface power mgmt. 3=off */
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Aspd = 1<<4,
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Adet = 1<<0, /* device detection */
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};
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#define sstatus scr0
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#define sctl scr2
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#define serror scr1
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#define sactive scr3
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typedef struct {
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uint32_t list; /* PxCLB must be 1kb aligned. */
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uint32_t listhi;
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uint32_t fis; /* 256-byte aligned */
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uint32_t fishi;
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uint32_t isr;
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uint32_t ie; /* interrupt enable */
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uint32_t cmd;
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uint32_t res1;
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uint32_t task;
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uint32_t sig;
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uint32_t scr0;
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uint32_t scr2;
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uint32_t scr1;
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uint32_t scr3;
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uint32_t ci; /* command issue */
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uint32_t ntf;
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uint8_t res2[8];
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uint32_t vendor;
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} Aport;
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enum {
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/*
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* Aport sstatus bits (actually states):
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* 11-8 interface power management
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* 7-4 current interface speed (generation #)
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* 3-0 device detection
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*/
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Intslumber = 0x600,
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Intpartpwr = 0x200,
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Intactive = 0x100,
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Intpm = 0xf00,
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Devphyoffline = 4,
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Devphycomm = 2, /* phy communication established */
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Devpresent = 1,
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Devdet = Devpresent | Devphycomm | Devphyoffline,
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};
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/* in host's memory; not memory mapped */
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typedef struct {
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uint8_t *base;
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uint8_t *d;
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uint8_t *p;
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uint8_t *r;
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uint8_t *u;
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uint32_t *devicebits;
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} Afis;
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enum {
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Lprdtl = 1<<16, /* physical region descriptor table len */
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Lpmp = 1<<12, /* port multiplier port */
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Lclear = 1<<10, /* clear busy on R_OK */
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Lbist = 1<<9,
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Lreset = 1<<8,
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Lpref = 1<<7, /* prefetchable */
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Lwrite = 1<<6,
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Latapi = 1<<5,
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Lcfl = 1<<0, /* command fis length in double words */
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};
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/* in hosts memory; memory mapped */
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typedef struct {
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uint32_t flags;
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uint32_t len;
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uint32_t ctab;
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uint32_t ctabhi;
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uint8_t reserved[16];
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} Alist;
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typedef struct {
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uint32_t dba;
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uint32_t dbahi;
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uint32_t pad;
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uint32_t count;
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} Aprdt;
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typedef struct {
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uint8_t cfis[0x40];
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uint8_t atapi[0x10];
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uint8_t pad[0x30];
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Aprdt prdt;
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} Actab;
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enum {
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Ferror = 1,
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Fdone = 2,
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};
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enum {
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Dllba = 1,
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Dsmart = 1<<1,
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Dpower = 1<<2,
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Dnop = 1<<3,
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Datapi = 1<<4,
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Datapi16= 1<<5,
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};
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typedef struct {
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QLock;
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Rendez;
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uint8_t flag;
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uint8_t feat;
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uint8_t smart;
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Afis fis;
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Alist *list;
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Actab *ctab;
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} Aportm;
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typedef struct {
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Aport *p;
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Aportm *pm;
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} Aportc;
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