330 lines
8.6 KiB
C
330 lines
8.6 KiB
C
/*
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* This file is part of the UCB release of Plan 9. It is subject to the license
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* terms in the LICENSE file found in the top-level directory of this
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* distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
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* part of the UCB release of Plan 9, including this file, may be copied,
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* modified, propagated, or distributed except according to the terms contained
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* in the LICENSE file.
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*/
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#include <u.h>
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#include <lib9.h>
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#include <bio.h>
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#include "pci.h"
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#include "vga.h"
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/*
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* #9 Ticket to Ride IV.
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*/
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typedef struct {
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Pcidev* pci;
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uint32_t io;
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uint8_t* mmio;
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uint32_t ioreg[13];
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uint32_t g[25];
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uint32_t w[25];
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} T2r4;
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enum { /* memory mapped global registers */
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IntVcnt = 0x20/4, /* vertical interrupt counter */
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IntHcnt = 0x24/4, /* horizontal interrupt counter */
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DbAdr = 0x28/4, /* display start address */
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DbPtch = 0x2C/4, /* display pitch */
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CrtHac = 0x30/4, /* horizontal active line width */
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CrtHbl = 0x34/4, /* horizontal blank width */
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CrtHfp = 0x38/4, /* horizontal front porch */
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CrtHs = 0x3C/4, /* horizontal sync width */
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CrtVac = 0x40/4, /* vertical active field width */
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CrtVbl = 0x44/4, /* vertical blank width */
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CrtVfp = 0x48/4, /* vertical front porch */
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CrtVs = 0x4C/4, /* vertical sync width */
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CrtLcnt = 0x50/4, /* CRT line counter */
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CrtZoom = 0x54/4, /* display zoom factor */
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Crt1con = 0x58/4, /* CRT configuration register 1 */
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Crt2con = 0x5C/4, /* CRT configuration register 2 */
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DbAdr2 = 0x60/4, /* CRT display start address 2 */
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};
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enum { /* memory windows registers */
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Mw0Ctrl = 0x00/4, /* memory window 0 control */
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Mw0Ad = 0x04/4, /* memory window 0 address */
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Mw0Sz = 0x08/4, /* memory window 0 size */
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Mw0Org = 0x10/4, /* memory window 0 origin */
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Mw0Mask = 0x24/4, /* Memory window 0 plane mask */
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Mw1Ctlr = 0x28/4, /* memory window 1 control */
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Mw1Ad = 0x2C/4, /* memory window 1 address */
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Mw1Sz = 0x30/4, /* memory window 1 size */
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Mw1Org = 0x38/4, /* memory window 1 origin */
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Mw1Mask = 0x4C/4, /* Memory window 1 plane mask */
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MwcFcnt = 0x50/4, /* memory window cache flush counter */
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MwcFlsh = 0x54/4, /* manual cache flush */
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YuvLi = 0x58/4, /* YUV LUT index */
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YuvLa = 0x5C/4, /* YUV LUT address */
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MwCtrl = 0x60/4, /* memory window 0 and 1 control */
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};
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enum {
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IndexLo = 4,
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IndexHi = 5,
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Data = 6,
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IndexCtl = 7,
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};
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static uint8_t
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_rgb524xi(Vga* vga, int index)
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{
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uint32_t *mmio;
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mmio = (uint32_t*)((T2r4*)vga->private)->mmio;
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mmio[IndexLo] = index & 0xFF;
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mmio[IndexHi] = (index>>8) & 0xFF;
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return mmio[Data];
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}
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static void
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_rgb524xo(Vga* vga, int index, uint8_t data)
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{
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uint32_t *mmio;
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mmio = (uint32_t*)((T2r4*)vga->private)->mmio;
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mmio[IndexLo] = index & 0xFF;
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mmio[IndexHi] = (index>>8) & 0xFF;
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mmio[Data] = data;
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}
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static void
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snarf(Vga* vga, Ctlr* ctlr)
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{
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uint32_t *mmio;
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int f, i, x;
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Pcidev *p;
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T2r4 *t2r4;
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uint32_t *rp;
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if(vga->private == nil){
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vga->private = alloc(sizeof(T2r4));
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if((p = pcimatch(0, 0x105D, 0)) == nil)
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error("%s: not found\n", ctlr->name);
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switch(p->did){
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case 0x5348: /* */
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break;
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default:
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error("%s: not found\n", ctlr->name);
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}
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if((f = sys_open("#v/vgactl", OWRITE)) < 0)
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error("%s: can't open vgactl\n", ctlr->name);
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if(jehanne_write(f, "type t2r4", 9) != 9)
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error("%s: can't set type\n", ctlr->name);
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sys_close(f);
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mmio = segattach(0, "t2r4mmio", 0, p->mem[4].size);
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if(mmio == (void*)-1)
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error("%s: can't attach mmio segment\n", ctlr->name);
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t2r4 = vga->private;
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t2r4->pci = p;
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t2r4->io = p->mem[5].bar & ~0x0F;
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t2r4->mmio = (uint8_t*)mmio;
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}
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t2r4 = vga->private;
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for(i = 0; i < nelem(t2r4->ioreg); i++)
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t2r4->ioreg[i] = inportl(t2r4->io+(i*4));
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x = t2r4->ioreg[7] & 0xFF00001F; /* config1 */
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outportl(t2r4->io+0x1C, x|0x00331F10);
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x = t2r4->ioreg[8] & 0xFF0FFFFF; /* config2 */
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outportl(t2r4->io+0x20, x|0x00100000);
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x = inportl(t2r4->io+0x30) & 0xFF; /* vgactl */
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outportl(t2r4->io+0x30, x|0x82);
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rp = (uint32_t*)t2r4->mmio;
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for(i = 0; i < nelem(t2r4->g); i++)
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t2r4->g[i] = *rp++;
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rp = (uint32_t*)(t2r4->mmio+8192);
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for(i = 0; i < nelem(t2r4->w); i++)
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t2r4->w[i] = *rp++;
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vga->vma = vga->vmz = t2r4->pci->mem[0].size;
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ctlr->flag |= Hlinear;
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/*
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* Currently, the RGB524 has no need of a snarf
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* routine so this will be called before any RGB524 code.
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*/
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if(vga->ramdac && strncmp(vga->ramdac->name, "rgb524mn", 8) == 0){
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rgb524mnxi = _rgb524xi;
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rgb524mnxo = _rgb524xo;
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}
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ctlr->flag |= Fsnarf;
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}
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static void
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options(Vga* vga, Ctlr* ctlr)
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{
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USED(vga);
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ctlr->flag |= Foptions;
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}
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static void
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init(Vga* vga, Ctlr* ctlr)
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{
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char *val;
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T2r4 *t2r4;
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int crtclocks, zoom;
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t2r4 = vga->private;
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crtclocks = 64/vga->mode->z;
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zoom = 1;
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if((val = dbattr(vga->mode->attr, "zoom")) && strtol(val, 0, 0))
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zoom = 2;
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t2r4->g[DbAdr] = 0;
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switch(vga->mode->z){
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case 8:
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t2r4->g[DbPtch] = vga->mode->x*1;
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break;
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case 16:
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t2r4->g[DbPtch] = vga->mode->x*2;
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break;
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case 32:
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t2r4->g[DbPtch] = vga->mode->x*4;
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break;
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}
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t2r4->g[CrtHac] = vga->mode->x/crtclocks;
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t2r4->g[CrtHbl] = (vga->mode->ht-vga->mode->x)/crtclocks;
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if(vga->mode->shs == 0)
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vga->mode->shs = vga->mode->shb;
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t2r4->g[CrtHfp] = (vga->mode->shs-vga->mode->x)/crtclocks;
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if(vga->mode->ehs == 0)
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vga->mode->ehs = vga->mode->ehb;
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t2r4->g[CrtHs] = (vga->mode->ehs-vga->mode->shs)/crtclocks;
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t2r4->g[CrtVac] = vga->mode->y * zoom;
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t2r4->g[CrtVbl] = (vga->mode->vt-vga->mode->y) * zoom;
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t2r4->g[CrtVfp] = (vga->mode->vrs-vga->mode->y) * zoom;
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t2r4->g[CrtVs] = (vga->mode->vre-vga->mode->vrs) * zoom;
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t2r4->g[CrtZoom] = 0;
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/*
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* Turn on the syncs and video.
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* Bts (bit 0x100) is digital RGB output enable. If there's
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* a flat-panel then this is hopefully already set by the BIOS,
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* so don't touch it. (It's possible that bit 0 of SoftSw
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* indicates flat-panel or CRT).
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*/
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t2r4->g[Crt1con] &= 0x00000100;
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t2r4->g[Crt1con] |= 0x70;
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t2r4->g[Crt2con] = 0x20000100;
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if(zoom == 2)
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t2r4->g[CrtZoom] = 1;
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t2r4->w[Mw0Ctrl] = 0;
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t2r4->w[Mw0Sz] = 0x0D; /* 32MB */
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t2r4->w[Mw0Org] = 0;
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t2r4->w[Mw0Mask] = 0xFFFFFFFF;
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if(vga->linear && (ctlr->flag & Hlinear))
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ctlr->flag |= Ulinear;
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ctlr->flag |= Finit;
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}
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static void
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load(Vga* vga, Ctlr* ctlr)
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{
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T2r4 *t2r4;
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uint32_t *g, *w;
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t2r4 = vga->private;
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g = (uint32_t*)t2r4->mmio;
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g[DbAdr] = t2r4->g[DbAdr];
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g[DbPtch] = t2r4->g[DbPtch];
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g[CrtHac] = t2r4->g[CrtHac];
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g[CrtHbl] = t2r4->g[CrtHbl];
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g[CrtHfp] = t2r4->g[CrtHfp];
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g[CrtHs] = t2r4->g[CrtHs];
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g[CrtVac] = t2r4->g[CrtVac];
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g[CrtVbl] = t2r4->g[CrtVbl];
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g[CrtVfp] = t2r4->g[CrtVfp];
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g[CrtVs] = t2r4->g[CrtVs];
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g[Crt1con] = t2r4->g[Crt1con];
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g[Crt2con] = t2r4->g[Crt2con];
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g[CrtZoom] = t2r4->g[CrtZoom];
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w = (uint32_t*)(t2r4->mmio+8192);
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w[Mw0Ctrl] = t2r4->w[Mw0Ctrl];
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w[Mw0Sz] = t2r4->w[Mw0Sz];
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w[Mw0Org] = t2r4->w[Mw0Org];
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w[Mw0Mask] = t2r4->w[Mw0Mask];
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if(t2r4->g[CrtZoom])
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outportl(t2r4->io+0x30, 0xA2); /* vgactl */
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else
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outportl(t2r4->io+0x30, 0x82); /* vgactl */
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outportl(t2r4->io+0x24, 0x211BF030); /* sgram */
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sleep(500);
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outportl(t2r4->io+0x24, 0xA11BF030); /* sgram */
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ctlr->flag |= Fload;
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}
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static void
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dump(Vga* vga, Ctlr* ctlr)
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{
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int i;
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T2r4 *t2r4;
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t2r4 = vga->private;
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Bprint(&stdout, "\n");
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Bprint(&stdout, "%s ioreg\t\t%8.8luX\n", ctlr->name, t2r4->io);
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Bprint(&stdout, "%s rbase_g\t%8.8luX\n", ctlr->name, t2r4->ioreg[0]);
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Bprint(&stdout, "%s rbase_w\t%8.8luX\n", ctlr->name, t2r4->ioreg[1]);
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Bprint(&stdout, "%s rbase_d\t%8.8luX\n", ctlr->name, t2r4->ioreg[2]);
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Bprint(&stdout, "%s rbase_i\t%8.8luX\n", ctlr->name, t2r4->ioreg[4]);
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Bprint(&stdout, "%s rbase_e\t%8.8luX\n", ctlr->name, t2r4->ioreg[5]);
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Bprint(&stdout, "%s id\t\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[6]);
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Bprint(&stdout, "%s config1\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[7]);
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Bprint(&stdout, "%s config2\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[8]);
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Bprint(&stdout, "%s sgram\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[9]);
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Bprint(&stdout, "%s softsw\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[10]);
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Bprint(&stdout, "%s ddc\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[11]);
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Bprint(&stdout, "%s vgactl\t\t%8.8luX\n", ctlr->name, t2r4->ioreg[12]);
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Bprint(&stdout, "\n");
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for(i = 0; i < nelem(t2r4->g); i++)
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Bprint(&stdout, "%s g reg0x%2.2uX\t\t%8.8luX\n",
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ctlr->name, i*4, t2r4->g[i]);
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Bprint(&stdout, "\n");
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for(i = 0; i < nelem(t2r4->w); i++)
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Bprint(&stdout, "%s w reg0x%2.2uX\t\t%8.8luX\n",
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ctlr->name, i*4, t2r4->w[i]);
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}
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Ctlr t2r4 = {
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"t2r4", /* name */
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snarf, /* snarf */
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options, /* options */
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init, /* init */
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load, /* load */
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dump, /* dump */
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};
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Ctlr t2r4hwgc = {
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"t2r4hwgc", /* name */
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0, /* snarf */
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0, /* options */
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0, /* init */
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0, /* load */
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0, /* dump */
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};
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